reg4.vhd

用VHDL 语言描述频率计的设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG4 IS
  PORT(LOAD:IN STD_LOGIC;
       DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
ARCHITECTURE ONE OF REG4 IS
  BEGIN
    PROCESS(LOAD)
      BEGIN 
        IF LOAD'EVENT AND LOAD='1'THEN DOUT<=DIN;
        END IF;
    END PROCESS;
END ONE;