testfre.tan.qmsg

用VHDL 语言描述频率计的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 14 20:38:39 2007 " "Info: Processing started: Thu Jun 14 20:38:39 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off TESTFRE -c TESTFRE --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off TESTFRE -c TESTFRE --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLKK " "Info: Assuming node \"CLKK\" is an undefined clock" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLKK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLKK register register div2clk div2clk 275.03 MHz Internal " "Info: Clock \"CLKK\" Internal fmax is restricted to 275.03 MHz between source register \"div2clk\" and destination register \"div2clk\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.026 ns + Longest register register " "Info: + Longest register to register delay is 1.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div2clk 1 REG LC_X1_Y9_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "" { div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.478 ns) 1.026 ns div2clk 2 REG LC_X1_Y9_N2 4 " "Info: 2: + IC(0.548 ns) + CELL(0.478 ns) = 1.026 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "1.026 ns" { div2clk div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 46.59 % ) " "Info: Total cell delay = 0.478 ns ( 46.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.548 ns ( 53.41 % ) " "Info: Total interconnect delay = 0.548 ns ( 53.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "1.026 ns" { div2clk div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.026 ns" { div2clk div2clk } { 0.000ns 0.548ns } { 0.000ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKK destination 6.795 ns + Shortest register " "Info: + Shortest clock path from clock \"CLKK\" to destination register is 6.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKK 1 CLK PIN_11 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'CLKK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "" { CLKK } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.615 ns) + CELL(0.711 ns) 6.795 ns div2clk 2 REG LC_X1_Y9_N2 4 " "Info: 2: + IC(4.615 ns) + CELL(0.711 ns) = 6.795 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "5.326 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 32.08 % ) " "Info: Total cell delay = 2.180 ns ( 32.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 67.92 % ) " "Info: Total interconnect delay = 4.615 ns ( 67.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "6.795 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.795 ns" { CLKK CLKK~out0 div2clk } { 0.000ns 0.000ns 4.615ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKK source 6.795 ns - Longest register " "Info: - Longest clock path from clock \"CLKK\" to source register is 6.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKK 1 CLK PIN_11 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'CLKK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "" { CLKK } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.615 ns) + CELL(0.711 ns) 6.795 ns div2clk 2 REG LC_X1_Y9_N2 4 " "Info: 2: + IC(4.615 ns) + CELL(0.711 ns) = 6.795 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "5.326 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 32.08 % ) " "Info: Total cell delay = 2.180 ns ( 32.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 67.92 % ) " "Info: Total interconnect delay = 4.615 ns ( 67.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "6.795 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.795 ns" { CLKK CLKK~out0 div2clk } { 0.000ns 0.000ns 4.615ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "6.795 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.795 ns" { CLKK CLKK~out0 div2clk } { 0.000ns 0.000ns 4.615ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "6.795 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.795 ns" { CLKK CLKK~out0 div2clk } { 0.000ns 0.000ns 4.615ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "1.026 ns" { div2clk div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.026 ns" { div2clk div2clk } { 0.000ns 0.548ns } { 0.000ns 0.478ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "6.795 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.795 ns" { CLKK CLKK~out0 div2clk } { 0.000ns 0.000ns 4.615ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "6.795 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.795 ns" { CLKK CLKK~out0 div2clk } { 0.000ns 0.000ns 4.615ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "" { div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { div2clk } {  } {  } } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}