hh.tan.summary

用VHDL 语言描述频率计的设计

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.829 ns
From           : REG4:R1|DOUT[3]
To             : LED0[2]
From Clock     : CLK1
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'UCLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : CNT10:C2|SS[0]
To             : CNT10:C2|SS[1]
From Clock     : UCLK
To Clock       : UCLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK1'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : TESTFRE:T|div2clk
To             : TESTFRE:T|div2clk
From Clock     : CLK1
To Clock       : CLK1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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