sm.vhd

用VHDL 语言描述频率计的设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SM IS
 PORT(I:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE ONE OF SM IS
 BEGIN 
  PROCESS(I)
   BEGIN
    CASE I IS
     WHEN "0001"=>O<="01100000";
     WHEN "0010"=>O<="11011010";
     WHEN "0011"=>O<="11110010";
     WHEN "0100"=>O<="01100110";
     WHEN "0101"=>O<="10110110";
     WHEN "0110"=>O<="10111110";
     WHEN "0111"=>O<="11100000";
     WHEN "1000"=>O<="11111110";
     WHEN "1001"=>O<="11110110";
     WHEN OTHERS=>O<="11111100";
END CASE;
END PROCESS;
END;