hh.fit.eqn

用VHDL 语言描述频率计的设计

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--D1L1 is SM:SM1|O[1]~212 at LC_X8_Y5_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_DOUT[0]_qfbk = C1_DOUT[0];
D1L1 = C1_DOUT[1] & !C1_DOUT[3] & (!C1_DOUT[0]_qfbk # !C1_DOUT[2]) # !C1_DOUT[1] & (C1_DOUT[2] $ (C1_DOUT[3]));

--C1_DOUT[0] is REG4:R1|DOUT[0] at LC_X8_Y5_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_DOUT[0] = DFFEAS(D1L1, !GLOBAL(E1_div2clk), VCC, , , B1_SS[0], , , VCC);


--D1L2 is SM:SM1|O[2]~213 at LC_X8_Y5_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_DOUT[1]_qfbk = C1_DOUT[1];
D1L2 = !C1_DOUT[3] & (C1_DOUT[2] & C1_DOUT[1]_qfbk & C1_DOUT[0] # !C1_DOUT[2] & (C1_DOUT[1]_qfbk # C1_DOUT[0]));

--C1_DOUT[1] is REG4:R1|DOUT[1] at LC_X8_Y5_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_DOUT[1] = DFFEAS(D1L2, !GLOBAL(E1_div2clk), VCC, , , B1_SS[1], , , VCC);


--D1L3 is SM:SM1|O[3]~214 at LC_X8_Y5_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_DOUT[2]_qfbk = C1_DOUT[2];
D1L3 = C1_DOUT[1] & !C1_DOUT[3] & (C1_DOUT[0]) # !C1_DOUT[1] & (C1_DOUT[2]_qfbk & !C1_DOUT[3] # !C1_DOUT[2]_qfbk & (C1_DOUT[0]));

--C1_DOUT[2] is REG4:R1|DOUT[2] at LC_X8_Y5_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_DOUT[2] = DFFEAS(D1L3, !GLOBAL(E1_div2clk), VCC, , , B1_SS[2], , , VCC);


--D1L4 is SM:SM1|O[4]~215 at LC_X8_Y5_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_DOUT[3]_qfbk = C1_DOUT[3];
D1L4 = !C1_DOUT[3]_qfbk & (C1_DOUT[1] & C1_DOUT[2] & C1_DOUT[0] # !C1_DOUT[1] & (C1_DOUT[2] $ C1_DOUT[0]));

--C1_DOUT[3] is REG4:R1|DOUT[3] at LC_X8_Y5_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_DOUT[3] = DFFEAS(D1L4, !GLOBAL(E1_div2clk), VCC, , , B1_SS[3], , , VCC);


--D1L5 is SM:SM1|O[5]~216 at LC_X8_Y5_N4
--operation mode is normal

D1L5 = C1_DOUT[1] & !C1_DOUT[3] & !C1_DOUT[2] & !C1_DOUT[0];


--D1L6 is SM:SM1|O[6]~217 at LC_X8_Y5_N7
--operation mode is normal

D1L6 = !C1_DOUT[3] & C1_DOUT[2] & (C1_DOUT[1] $ C1_DOUT[0]);


--D1L7 is SM:SM1|O[7]~218 at LC_X8_Y5_N2
--operation mode is normal

D1L7 = !C1_DOUT[1] & !C1_DOUT[3] & (C1_DOUT[2] $ C1_DOUT[0]);


--D2L1 is SM:SM2|O[1]~212 at LC_X25_Y9_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[0]_qfbk = C2_DOUT[0];
D2L1 = C2_DOUT[1] & !C2_DOUT[3] & (!C2_DOUT[0]_qfbk # !C2_DOUT[2]) # !C2_DOUT[1] & (C2_DOUT[2] $ (C2_DOUT[3]));

--C2_DOUT[0] is REG4:R2|DOUT[0] at LC_X25_Y9_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[0] = DFFEAS(D2L1, !GLOBAL(E1_div2clk), VCC, , , B2_SS[0], , , VCC);


--D2L2 is SM:SM2|O[2]~213 at LC_X25_Y9_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[1]_qfbk = C2_DOUT[1];
D2L2 = !C2_DOUT[3] & (C2_DOUT[0] & (C2_DOUT[1]_qfbk # !C2_DOUT[2]) # !C2_DOUT[0] & !C2_DOUT[2] & C2_DOUT[1]_qfbk);

--C2_DOUT[1] is REG4:R2|DOUT[1] at LC_X25_Y9_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[1] = DFFEAS(D2L2, !GLOBAL(E1_div2clk), VCC, , , B2_SS[1], , , VCC);


--D2L3 is SM:SM2|O[3]~214 at LC_X25_Y9_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[2]_qfbk = C2_DOUT[2];
D2L3 = C2_DOUT[1] & C2_DOUT[0] & !C2_DOUT[3] # !C2_DOUT[1] & (C2_DOUT[2]_qfbk & (!C2_DOUT[3]) # !C2_DOUT[2]_qfbk & C2_DOUT[0]);

--C2_DOUT[2] is REG4:R2|DOUT[2] at LC_X25_Y9_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[2] = DFFEAS(D2L3, !GLOBAL(E1_div2clk), VCC, , , B2_SS[2], , , VCC);


--D2L4 is SM:SM2|O[4]~215 at LC_X25_Y9_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[3]_qfbk = C2_DOUT[3];
D2L4 = !C2_DOUT[3]_qfbk & (C2_DOUT[0] & (C2_DOUT[2] $ !C2_DOUT[1]) # !C2_DOUT[0] & C2_DOUT[2] & !C2_DOUT[1]);

--C2_DOUT[3] is REG4:R2|DOUT[3] at LC_X25_Y9_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[3] = DFFEAS(D2L4, !GLOBAL(E1_div2clk), VCC, , , B2_SS[3], , , VCC);


--D2L5 is SM:SM2|O[5]~216 at LC_X25_Y9_N2
--operation mode is normal

D2L5 = !C2_DOUT[0] & !C2_DOUT[2] & !C2_DOUT[3] & C2_DOUT[1];


--D2L6 is SM:SM2|O[6]~217 at LC_X25_Y9_N9
--operation mode is normal

D2L6 = C2_DOUT[2] & !C2_DOUT[3] & (C2_DOUT[0] $ C2_DOUT[1]);


--D2L7 is SM:SM2|O[7]~218 at LC_X25_Y9_N5
--operation mode is normal

D2L7 = !C2_DOUT[3] & !C2_DOUT[1] & (C2_DOUT[0] $ C2_DOUT[2]);


--D3L1 is SM:SM3|O[1]~212 at LC_X26_Y7_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C3_DOUT[0]_qfbk = C3_DOUT[0];
D3L1 = C3_DOUT[1] & !C3_DOUT[3] & (!C3_DOUT[2] # !C3_DOUT[0]_qfbk) # !C3_DOUT[1] & (C3_DOUT[3] $ (C3_DOUT[2]));

--C3_DOUT[0] is REG4:R3|DOUT[0] at LC_X26_Y7_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C3_DOUT[0] = DFFEAS(D3L1, !GLOBAL(E1_div2clk), VCC, , , B3_SS[0], , , VCC);


--D3L2 is SM:SM3|O[2]~213 at LC_X26_Y7_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C3_DOUT[1]_qfbk = C3_DOUT[1];
D3L2 = !C3_DOUT[3] & (C3_DOUT[0] & (C3_DOUT[1]_qfbk # !C3_DOUT[2]) # !C3_DOUT[0] & C3_DOUT[1]_qfbk & !C3_DOUT[2]);

--C3_DOUT[1] is REG4:R3|DOUT[1] at LC_X26_Y7_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C3_DOUT[1] = DFFEAS(D3L2, !GLOBAL(E1_div2clk), VCC, , , B3_SS[1], , , VCC);


--D3L3 is SM:SM3|O[3]~214 at LC_X26_Y7_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C3_DOUT[2]_qfbk = C3_DOUT[2];
D3L3 = C3_DOUT[1] & C3_DOUT[0] & !C3_DOUT[3] # !C3_DOUT[1] & (C3_DOUT[2]_qfbk & (!C3_DOUT[3]) # !C3_DOUT[2]_qfbk & C3_DOUT[0]);

--C3_DOUT[2] is REG4:R3|DOUT[2] at LC_X26_Y7_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C3_DOUT[2] = DFFEAS(D3L3, !GLOBAL(E1_div2clk), VCC, , , B3_SS[2], , , VCC);


--D3L4 is SM:SM3|O[4]~215 at LC_X26_Y7_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C3_DOUT[3]_qfbk = C3_DOUT[3];
D3L4 = !C3_DOUT[3]_qfbk & (C3_DOUT[0] & (C3_DOUT[2] $ !C3_DOUT[1]) # !C3_DOUT[0] & C3_DOUT[2] & !C3_DOUT[1]);

--C3_DOUT[3] is REG4:R3|DOUT[3] at LC_X26_Y7_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C3_DOUT[3] = DFFEAS(D3L4, !GLOBAL(E1_div2clk), VCC, , , B3_SS[3], , , VCC);


--D3L5 is SM:SM3|O[5]~216 at LC_X26_Y7_N5
--operation mode is normal

D3L5 = !C3_DOUT[0] & !C3_DOUT[2] & !C3_DOUT[3] & C3_DOUT[1];


--D3L6 is SM:SM3|O[6]~217 at LC_X26_Y7_N9
--operation mode is normal

D3L6 = C3_DOUT[2] & !C3_DOUT[3] & (C3_DOUT[0] $ C3_DOUT[1]);


--D3L7 is SM:SM3|O[7]~218 at LC_X26_Y7_N2
--operation mode is normal

D3L7 = !C3_DOUT[3] & !C3_DOUT[1] & (C3_DOUT[0] $ C3_DOUT[2]);


--D4L1 is SM:SM4|O[1]~212 at LC_X22_Y5_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C4_DOUT[0]_qfbk = C4_DOUT[0];
D4L1 = C4_DOUT[2] & !C4_DOUT[3] & (!C4_DOUT[1] # !C4_DOUT[0]_qfbk) # !C4_DOUT[2] & (C4_DOUT[3] $ (C4_DOUT[1]));

--C4_DOUT[0] is REG4:R4|DOUT[0] at LC_X22_Y5_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C4_DOUT[0] = DFFEAS(D4L1, !GLOBAL(E1_div2clk), VCC, , , B4_SS[0], , , VCC);


--D4L2 is SM:SM4|O[2]~213 at LC_X22_Y5_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C4_DOUT[1]_qfbk = C4_DOUT[1];
D4L2 = !C4_DOUT[3] & (C4_DOUT[2] & C4_DOUT[1]_qfbk & C4_DOUT[0] # !C4_DOUT[2] & (C4_DOUT[1]_qfbk # C4_DOUT[0]));

--C4_DOUT[1] is REG4:R4|DOUT[1] at LC_X22_Y5_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C4_DOUT[1] = DFFEAS(D4L2, !GLOBAL(E1_div2clk), VCC, , , B4_SS[1], , , VCC);


--D4L3 is SM:SM4|O[3]~214 at LC_X22_Y5_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C4_DOUT[2]_qfbk = C4_DOUT[2];
D4L3 = C4_DOUT[1] & C4_DOUT[0] & !C4_DOUT[3] # !C4_DOUT[1] & (C4_DOUT[2]_qfbk & (!C4_DOUT[3]) # !C4_DOUT[2]_qfbk & C4_DOUT[0]);

--C4_DOUT[2] is REG4:R4|DOUT[2] at LC_X22_Y5_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C4_DOUT[2] = DFFEAS(D4L3, !GLOBAL(E1_div2clk), VCC, , , B4_SS[2], , , VCC);


--D4L4 is SM:SM4|O[4]~215 at LC_X22_Y5_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C4_DOUT[3]_qfbk = C4_DOUT[3];
D4L4 = !C4_DOUT[3]_qfbk & (C4_DOUT[2] & (C4_DOUT[0] $ !C4_DOUT[1]) # !C4_DOUT[2] & C4_DOUT[0] & !C4_DOUT[1]);

--C4_DOUT[3] is REG4:R4|DOUT[3] at LC_X22_Y5_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C4_DOUT[3] = DFFEAS(D4L4, !GLOBAL(E1_div2clk), VCC, , , B4_SS[3], , , VCC);


--D4L5 is SM:SM4|O[5]~216 at LC_X22_Y5_N6
--operation mode is normal

D4L5 = !C4_DOUT[2] & !C4_DOUT[0] & !C4_DOUT[3] & C4_DOUT[1];


--D4L6 is SM:SM4|O[6]~217 at LC_X22_Y5_N7
--operation mode is normal

D4L6 = C4_DOUT[2] & !C4_DOUT[3] & (C4_DOUT[0] $ C4_DOUT[1]);


--D4L7 is SM:SM4|O[7]~218 at LC_X22_Y5_N2
--operation mode is normal

D4L7 = !C4_DOUT[3] & !C4_DOUT[1] & (C4_DOUT[2] $ C4_DOUT[0]);


--B1_SS[0] is CNT10:C0|SS[0] at LC_X8_Y6_N2
--operation mode is normal

B1_SS[0]_lut_out = !B1_SS[0];
B1_SS[0] = DFFEAS(B1_SS[0]_lut_out, GLOBAL(UCLK), !GLOBAL(E1_RSTC), , E1_div2clk, , , , );


--E1_div2clk is TESTFRE:T|div2clk at LC_X10_Y6_N2
--operation mode is normal

E1_div2clk_lut_out = !E1_div2clk;
E1_div2clk = DFFEAS(E1_div2clk_lut_out, CLK1, VCC, , , , , , );


--B1_SS[1] is CNT10:C0|SS[1] at LC_X8_Y6_N8
--operation mode is normal

B1_SS[1]_lut_out = B1_SS[1] & (!B1_SS[0]) # !B1_SS[1] & B1_SS[0] & (B1_SS[2] # !B1_SS[3]);
B1_SS[1] = DFFEAS(B1_SS[1]_lut_out, GLOBAL(UCLK), !GLOBAL(E1_RSTC), , E1_div2clk, , , , );


--B1_SS[2] is CNT10:C0|SS[2] at LC_X8_Y6_N6