hh.map.eqn

用VHDL 语言描述频率计的设计

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C1_DOUT[0] is REG4:R1|DOUT[0]
--operation mode is normal

C1_DOUT[0]_lut_out = B1_SS[0];
C1_DOUT[0] = DFFEAS(C1_DOUT[0]_lut_out, !E1_div2clk, VCC, , , , , , );


--C1_DOUT[1] is REG4:R1|DOUT[1]
--operation mode is normal

C1_DOUT[1]_lut_out = B1_SS[1];
C1_DOUT[1] = DFFEAS(C1_DOUT[1]_lut_out, !E1_div2clk, VCC, , , , , , );


--C1_DOUT[2] is REG4:R1|DOUT[2]
--operation mode is normal

C1_DOUT[2]_lut_out = B1_SS[2];
C1_DOUT[2] = DFFEAS(C1_DOUT[2]_lut_out, !E1_div2clk, VCC, , , , , , );


--C1_DOUT[3] is REG4:R1|DOUT[3]
--operation mode is normal

C1_DOUT[3]_lut_out = B1_SS[3];
C1_DOUT[3] = DFFEAS(C1_DOUT[3]_lut_out, !E1_div2clk, VCC, , , , , , );


--D1L1 is SM:SM1|O[1]~212
--operation mode is normal

D1L1 = C1_DOUT[1] & !C1_DOUT[3] & (!C1_DOUT[2] # !C1_DOUT[0]) # !C1_DOUT[1] & (C1_DOUT[2] $ C1_DOUT[3]);


--D1L2 is SM:SM1|O[2]~213
--operation mode is normal

D1L2 = !C1_DOUT[3] & (C1_DOUT[0] & (C1_DOUT[1] # !C1_DOUT[2]) # !C1_DOUT[0] & C1_DOUT[1] & !C1_DOUT[2]);


--D1L3 is SM:SM1|O[3]~214
--operation mode is normal

D1L3 = C1_DOUT[1] & C1_DOUT[0] & (!C1_DOUT[3]) # !C1_DOUT[1] & (C1_DOUT[2] & (!C1_DOUT[3]) # !C1_DOUT[2] & C1_DOUT[0]);


--D1L4 is SM:SM1|O[4]~215
--operation mode is normal

D1L4 = !C1_DOUT[3] & (C1_DOUT[0] & (C1_DOUT[1] $ !C1_DOUT[2]) # !C1_DOUT[0] & !C1_DOUT[1] & C1_DOUT[2]);


--D1L5 is SM:SM1|O[5]~216
--operation mode is normal

D1L5 = C1_DOUT[1] & !C1_DOUT[0] & !C1_DOUT[2] & !C1_DOUT[3];


--D1L6 is SM:SM1|O[6]~217
--operation mode is normal

D1L6 = C1_DOUT[2] & !C1_DOUT[3] & (C1_DOUT[0] $ C1_DOUT[1]);


--D1L7 is SM:SM1|O[7]~218
--operation mode is normal

D1L7 = !C1_DOUT[1] & !C1_DOUT[3] & (C1_DOUT[0] $ C1_DOUT[2]);


--C2_DOUT[0] is REG4:R2|DOUT[0]
--operation mode is normal

C2_DOUT[0]_lut_out = B2_SS[0];
C2_DOUT[0] = DFFEAS(C2_DOUT[0]_lut_out, !E1_div2clk, VCC, , , , , , );


--C2_DOUT[1] is REG4:R2|DOUT[1]
--operation mode is normal

C2_DOUT[1]_lut_out = B2_SS[1];
C2_DOUT[1] = DFFEAS(C2_DOUT[1]_lut_out, !E1_div2clk, VCC, , , , , , );


--C2_DOUT[2] is REG4:R2|DOUT[2]
--operation mode is normal

C2_DOUT[2]_lut_out = B2_SS[2];
C2_DOUT[2] = DFFEAS(C2_DOUT[2]_lut_out, !E1_div2clk, VCC, , , , , , );


--C2_DOUT[3] is REG4:R2|DOUT[3]
--operation mode is normal

C2_DOUT[3]_lut_out = B2_SS[3];
C2_DOUT[3] = DFFEAS(C2_DOUT[3]_lut_out, !E1_div2clk, VCC, , , , , , );


--D2L1 is SM:SM2|O[1]~212
--operation mode is normal

D2L1 = C2_DOUT[1] & !C2_DOUT[3] & (!C2_DOUT[2] # !C2_DOUT[0]) # !C2_DOUT[1] & (C2_DOUT[2] $ C2_DOUT[3]);


--D2L2 is SM:SM2|O[2]~213
--operation mode is normal

D2L2 = !C2_DOUT[3] & (C2_DOUT[0] & (C2_DOUT[1] # !C2_DOUT[2]) # !C2_DOUT[0] & C2_DOUT[1] & !C2_DOUT[2]);


--D2L3 is SM:SM2|O[3]~214
--operation mode is normal

D2L3 = C2_DOUT[1] & C2_DOUT[0] & (!C2_DOUT[3]) # !C2_DOUT[1] & (C2_DOUT[2] & (!C2_DOUT[3]) # !C2_DOUT[2] & C2_DOUT[0]);


--D2L4 is SM:SM2|O[4]~215
--operation mode is normal

D2L4 = !C2_DOUT[3] & (C2_DOUT[0] & (C2_DOUT[1] $ !C2_DOUT[2]) # !C2_DOUT[0] & !C2_DOUT[1] & C2_DOUT[2]);


--D2L5 is SM:SM2|O[5]~216
--operation mode is normal

D2L5 = C2_DOUT[1] & !C2_DOUT[0] & !C2_DOUT[2] & !C2_DOUT[3];


--D2L6 is SM:SM2|O[6]~217
--operation mode is normal

D2L6 = C2_DOUT[2] & !C2_DOUT[3] & (C2_DOUT[0] $ C2_DOUT[1]);


--D2L7 is SM:SM2|O[7]~218
--operation mode is normal

D2L7 = !C2_DOUT[1] & !C2_DOUT[3] & (C2_DOUT[0] $ C2_DOUT[2]);


--C3_DOUT[0] is REG4:R3|DOUT[0]
--operation mode is normal

C3_DOUT[0]_lut_out = B3_SS[0];
C3_DOUT[0] = DFFEAS(C3_DOUT[0]_lut_out, !E1_div2clk, VCC, , , , , , );


--C3_DOUT[1] is REG4:R3|DOUT[1]
--operation mode is normal

C3_DOUT[1]_lut_out = B3_SS[1];
C3_DOUT[1] = DFFEAS(C3_DOUT[1]_lut_out, !E1_div2clk, VCC, , , , , , );


--C3_DOUT[2] is REG4:R3|DOUT[2]
--operation mode is normal

C3_DOUT[2]_lut_out = B3_SS[2];
C3_DOUT[2] = DFFEAS(C3_DOUT[2]_lut_out, !E1_div2clk, VCC, , , , , , );


--C3_DOUT[3] is REG4:R3|DOUT[3]
--operation mode is normal

C3_DOUT[3]_lut_out = B3_SS[3];
C3_DOUT[3] = DFFEAS(C3_DOUT[3]_lut_out, !E1_div2clk, VCC, , , , , , );


--D3L1 is SM:SM3|O[1]~212
--operation mode is normal

D3L1 = C3_DOUT[1] & !C3_DOUT[3] & (!C3_DOUT[2] # !C3_DOUT[0]) # !C3_DOUT[1] & (C3_DOUT[2] $ C3_DOUT[3]);


--D3L2 is SM:SM3|O[2]~213
--operation mode is normal

D3L2 = !C3_DOUT[3] & (C3_DOUT[0] & (C3_DOUT[1] # !C3_DOUT[2]) # !C3_DOUT[0] & C3_DOUT[1] & !C3_DOUT[2]);


--D3L3 is SM:SM3|O[3]~214
--operation mode is normal

D3L3 = C3_DOUT[1] & C3_DOUT[0] & (!C3_DOUT[3]) # !C3_DOUT[1] & (C3_DOUT[2] & (!C3_DOUT[3]) # !C3_DOUT[2] & C3_DOUT[0]);


--D3L4 is SM:SM3|O[4]~215
--operation mode is normal

D3L4 = !C3_DOUT[3] & (C3_DOUT[0] & (C3_DOUT[1] $ !C3_DOUT[2]) # !C3_DOUT[0] & !C3_DOUT[1] & C3_DOUT[2]);


--D3L5 is SM:SM3|O[5]~216
--operation mode is normal

D3L5 = C3_DOUT[1] & !C3_DOUT[0] & !C3_DOUT[2] & !C3_DOUT[3];


--D3L6 is SM:SM3|O[6]~217
--operation mode is normal

D3L6 = C3_DOUT[2] & !C3_DOUT[3] & (C3_DOUT[0] $ C3_DOUT[1]);


--D3L7 is SM:SM3|O[7]~218
--operation mode is normal

D3L7 = !C3_DOUT[1] & !C3_DOUT[3] & (C3_DOUT[0] $ C3_DOUT[2]);


--C4_DOUT[0] is REG4:R4|DOUT[0]
--operation mode is normal

C4_DOUT[0]_lut_out = B4_SS[0];
C4_DOUT[0] = DFFEAS(C4_DOUT[0]_lut_out, !E1_div2clk, VCC, , , , , , );


--C4_DOUT[1] is REG4:R4|DOUT[1]
--operation mode is normal

C4_DOUT[1]_lut_out = B4_SS[1];
C4_DOUT[1] = DFFEAS(C4_DOUT[1]_lut_out, !E1_div2clk, VCC, , , , , , );


--C4_DOUT[2] is REG4:R4|DOUT[2]
--operation mode is normal

C4_DOUT[2]_lut_out = B4_SS[2];
C4_DOUT[2] = DFFEAS(C4_DOUT[2]_lut_out, !E1_div2clk, VCC, , , , , , );


--C4_DOUT[3] is REG4:R4|DOUT[3]
--operation mode is normal

C4_DOUT[3]_lut_out = B4_SS[3];
C4_DOUT[3] = DFFEAS(C4_DOUT[3]_lut_out, !E1_div2clk, VCC, , , , , , );


--D4L1 is SM:SM4|O[1]~212
--operation mode is normal

D4L1 = C4_DOUT[1] & !C4_DOUT[3] & (!C4_DOUT[2] # !C4_DOUT[0]) # !C4_DOUT[1] & (C4_DOUT[2] $ C4_DOUT[3]);


--D4L2 is SM:SM4|O[2]~213
--operation mode is normal

D4L2 = !C4_DOUT[3] & (C4_DOUT[0] & (C4_DOUT[1] # !C4_DOUT[2]) # !C4_DOUT[0] & C4_DOUT[1] & !C4_DOUT[2]);


--D4L3 is SM:SM4|O[3]~214
--operation mode is normal

D4L3 = C4_DOUT[1] & C4_DOUT[0] & (!C4_DOUT[3]) # !C4_DOUT[1] & (C4_DOUT[2] & (!C4_DOUT[3]) # !C4_DOUT[2] & C4_DOUT[0]);


--D4L4 is SM:SM4|O[4]~215
--operation mode is normal

D4L4 = !C4_DOUT[3] & (C4_DOUT[0] & (C4_DOUT[1] $ !C4_DOUT[2]) # !C4_DOUT[0] & !C4_DOUT[1] & C4_DOUT[2]);


--D4L5 is SM:SM4|O[5]~216
--operation mode is normal

D4L5 = C4_DOUT[1] & !C4_DOUT[0] & !C4_DOUT[2] & !C4_DOUT[3];


--D4L6 is SM:SM4|O[6]~217
--operation mode is normal

D4L6 = C4_DOUT[2] & !C4_DOUT[3] & (C4_DOUT[0] $ C4_DOUT[1]);


--D4L7 is SM:SM4|O[7]~218
--operation mode is normal

D4L7 = !C4_DOUT[1] & !C4_DOUT[3] & (C4_DOUT[0] $ C4_DOUT[2]);


--B1_SS[0] is CNT10:C0|SS[0]
--operation mode is normal

B1_SS[0]_lut_out = !B1_SS[0];
B1_SS[0] = DFFEAS(B1_SS[0]_lut_out, UCLK, !E1_RSTC, , E1_div2clk, , , , );


--E1_div2clk is TESTFRE:T|div2clk
--operation mode is normal

E1_div2clk_lut_out = !E1_div2clk;
E1_div2clk = DFFEAS(E1_div2clk_lut_out, CLK1, VCC, , , , , , );


--B1_SS[1] is CNT10:C0|SS[1]
--operation mode is normal

B1_SS[1]_lut_out = B1_SS[1] & (!B1_SS[0]) # !B1_SS[1] & B1_SS[0] & (B1_SS[2] # !B1_SS[3]);
B1_SS[1] = DFFEAS(B1_SS[1]_lut_out, UCLK, !E1_RSTC, , E1_div2clk, , , , );


--B1_SS[2] is CNT10:C0|SS[2]
--operation mode is normal

B1_SS[2]_lut_out = B1_SS[2] $ (B1_SS[0] & E1_div2clk & B1_SS[1]);
B1_SS[2] = DFFEAS(B1_SS[2]_lut_out, UCLK, !E1_RSTC, , , , , , );


--B1_SS[3] is CNT10:C0|SS[3]
--operation mode is normal

B1_SS[3]_lut_out = B1_SS[3] & (B1_SS[1] $ B1_SS[2] # !B1_SS[0]) # !B1_SS[3] & B1_SS[1] & B1_SS[2] & B1_SS[0];
B1_SS[3] = DFFEAS(B1_SS[3]_lut_out, UCLK, !E1_RSTC, , E1_div2clk, , , , );


--B2_SS[0] is CNT10:C1|SS[0]
--operation mode is normal

B2_SS[0]_lut_out = !B2_SS[0];
B2_SS[0] = DFFEAS(B2_SS[0]_lut_out, B1_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B2_SS[1] is CNT10:C1|SS[1]
--operation mode is normal

B2_SS[1]_lut_out = B2_SS[1] & (!B2_SS[0]) # !B2_SS[1] & B2_SS[0] & (B2_SS[2] # !B2_SS[3]);
B2_SS[1] = DFFEAS(B2_SS[1]_lut_out, B1_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B2_SS[2] is CNT10:C1|SS[2]
--operation mode is normal

B2_SS[2]_lut_out = B2_SS[2] $ (E1_div2clk & B2_SS[0] & B2_SS[1]);
B2_SS[2] = DFFEAS(B2_SS[2]_lut_out, B1_OUTY, !E1_RSTC, , , , , , );


--B2_SS[3] is CNT10:C1|SS[3]
--operation mode is normal

B2_SS[3]_lut_out = B2_SS[3] & (B2_SS[1] $ B2_SS[2] # !B2_SS[0]) # !B2_SS[3] & B2_SS[1] & B2_SS[2] & B2_SS[0];
B2_SS[3] = DFFEAS(B2_SS[3]_lut_out, B1_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B3_SS[0] is CNT10:C2|SS[0]
--operation mode is normal

B3_SS[0]_lut_out = !B3_SS[0];
B3_SS[0] = DFFEAS(B3_SS[0]_lut_out, B2_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B3_SS[1] is CNT10:C2|SS[1]
--operation mode is normal

B3_SS[1]_lut_out = B3_SS[1] & (!B3_SS[0]) # !B3_SS[1] & B3_SS[0] & (B3_SS[2] # !B3_SS[3]);
B3_SS[1] = DFFEAS(B3_SS[1]_lut_out, B2_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B3_SS[2] is CNT10:C2|SS[2]
--operation mode is normal

B3_SS[2]_lut_out = B3_SS[2] $ (E1_div2clk & B3_SS[0] & B3_SS[1]);
B3_SS[2] = DFFEAS(B3_SS[2]_lut_out, B2_OUTY, !E1_RSTC, , , , , , );


--B3_SS[3] is CNT10:C2|SS[3]
--operation mode is normal

B3_SS[3]_lut_out = B3_SS[3] & (B3_SS[1] $ B3_SS[2] # !B3_SS[0]) # !B3_SS[3] & B3_SS[1] & B3_SS[2] & B3_SS[0];
B3_SS[3] = DFFEAS(B3_SS[3]_lut_out, B2_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B4_SS[0] is CNT10:C3|SS[0]
--operation mode is normal

B4_SS[0]_lut_out = !B4_SS[0];
B4_SS[0] = DFFEAS(B4_SS[0]_lut_out, B3_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B4_SS[1] is CNT10:C3|SS[1]
--operation mode is normal

B4_SS[1]_lut_out = B4_SS[1] & (!B4_SS[0]) # !B4_SS[1] & B4_SS[0] & (B4_SS[2] # !B4_SS[3]);
B4_SS[1] = DFFEAS(B4_SS[1]_lut_out, B3_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B4_SS[2] is CNT10:C3|SS[2]
--operation mode is normal

B4_SS[2]_lut_out = B4_SS[2] $ (E1_div2clk & B4_SS[0] & B4_SS[1]);
B4_SS[2] = DFFEAS(B4_SS[2]_lut_out, B3_OUTY, !E1_RSTC, , , , , , );


--B4_SS[3] is CNT10:C3|SS[3]
--operation mode is normal

B4_SS[3]_lut_out = B4_SS[3] & (B4_SS[1] $ B4_SS[2] # !B4_SS[0]) # !B4_SS[3] & B4_SS[1] & B4_SS[2] & B4_SS[0];
B4_SS[3] = DFFEAS(B4_SS[3]_lut_out, B3_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--E1_RSTC is TESTFRE:T|RSTC
--operation mode is normal

E1_RSTC = !E1_div2clk & !CLK1;


--B1_OUTY is CNT10:C0|OUTY
--operation mode is normal

B1_OUTY_lut_out = B1_SS[0] & B1_SS[3] & !B1_SS[1] & !B1_SS[2];
B1_OUTY = DFFEAS(B1_OUTY_lut_out, UCLK, !E1_RSTC, , E1_div2clk, , , , );


--B2_OUTY is CNT10:C1|OUTY
--operation mode is normal

B2_OUTY_lut_out = B2_SS[0] & B2_SS[3] & !B2_SS[1] & !B2_SS[2];
B2_OUTY = DFFEAS(B2_OUTY_lut_out, B1_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--B3_OUTY is CNT10:C2|OUTY
--operation mode is normal

B3_OUTY_lut_out = B3_SS[0] & B3_SS[3] & !B3_SS[1] & !B3_SS[2];
B3_OUTY = DFFEAS(B3_OUTY_lut_out, B2_OUTY, !E1_RSTC, , E1_div2clk, , , , );


--UCLK is UCLK
--operation mode is input

UCLK = INPUT();


--CLK1 is CLK1
--operation mode is input

CLK1 = INPUT();


--LED0[0] is LED0[0]
--operation mode is output

LED0[0] = OUTPUT(GND);


--LED0[1] is LED0[1]
--operation mode is output

LED0[1] = OUTPUT(D1L1);


--LED0[2] is LED0[2]
--operation mode is output

LED0[2] = OUTPUT(!D1L2);


--LED0[3] is LED0[3]
--operation mode is output

LED0[3] = OUTPUT(!D1L3);


--LED0[4] is LED0[4]
--operation mode is output

LED0[4] = OUTPUT(!D1L4);


--LED0[5] is LED0[5]
--operation mode is output

LED0[5] = OUTPUT(!D1L5);


--LED0[6] is LED0[6]
--operation mode is output

LED0[6] = OUTPUT(!D1L6);


--LED0[7] is LED0[7]
--operation mode is output

LED0[7] = OUTPUT(!D1L7);


--LED1[0] is LED1[0]
--operation mode is output

LED1[0] = OUTPUT(GND);


--LED1[1] is LED1[1]
--operation mode is output

LED1[1] = OUTPUT(D2L1);


--LED1[2] is LED1[2]
--operation mode is output

LED1[2] = OUTPUT(!D2L2);


--LED1[3] is LED1[3]
--operation mode is output

LED1[3] = OUTPUT(!D2L3);


--LED1[4] is LED1[4]
--operation mode is output

LED1[4] = OUTPUT(!D2L4);


--LED1[5] is LED1[5]
--operation mode is output

LED1[5] = OUTPUT(!D2L5);


--LED1[6] is LED1[6]
--operation mode is output

LED1[6] = OUTPUT(!D2L6);


--LED1[7] is LED1[7]
--operation mode is output

LED1[7] = OUTPUT(!D2L7);


--LED2[0] is LED2[0]
--operation mode is output

LED2[0] = OUTPUT(GND);


--LED2[1] is LED2[1]
--operation mode is output

LED2[1] = OUTPUT(D3L1);


--LED2[2] is LED2[2]
--operation mode is output

LED2[2] = OUTPUT(!D3L2);


--LED2[3] is LED2[3]
--operation mode is output

LED2[3] = OUTPUT(!D3L3);


--LED2[4] is LED2[4]
--operation mode is output

LED2[4] = OUTPUT(!D3L4);


--LED2[5] is LED2[5]
--operation mode is output

LED2[5] = OUTPUT(!D3L5);


--LED2[6] is LED2[6]
--operation mode is output

LED2[6] = OUTPUT(!D3L6);


--LED2[7] is LED2[7]
--operation mode is output

LED2[7] = OUTPUT(!D3L7);


--LED3[0] is LED3[0]
--operation mode is output

LED3[0] = OUTPUT(GND);


--LED3[1] is LED3[1]
--operation mode is output

LED3[1] = OUTPUT(D4L1);


--LED3[2] is LED3[2]
--operation mode is output

LED3[2] = OUTPUT(!D4L2);


--LED3[3] is LED3[3]
--operation mode is output

LED3[3] = OUTPUT(!D4L3);


--LED3[4] is LED3[4]
--operation mode is output

LED3[4] = OUTPUT(!D4L4);


--LED3[5] is LED3[5]
--operation mode is output

LED3[5] = OUTPUT(!D4L5);


--LED3[6] is LED3[6]
--operation mode is output

LED3[6] = OUTPUT(!D4L6);


--LED3[7] is LED3[7]
--operation mode is output

LED3[7] = OUTPUT(!D4L7);