📄 hh.map.rpt
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+-----------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------+
; Total logic elements ; 65 ;
; -- Combinational with no register ; 29 ;
; -- Register only ; 16 ;
; -- Combinational with a register ; 20 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 43 ;
; -- 3 input functions ; 0 ;
; -- 2 input functions ; 1 ;
; -- 1 input functions ; 5 ;
; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 65 ;
; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 19 ;
; ; ;
; Total registers ; 36 ;
; I/O pins ; 34 ;
; Maximum fan-out node ; TESTFRE:T|div2clk ;
; Maximum fan-out ; 37 ;
; Total fan-out ; 293 ;
; Average fan-out ; 2.96 ;
+---------------------------------------------+-------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |hh ; 65 (0) ; 36 ; 0 ; 34 ; 0 ; 29 (0) ; 16 (0) ; 20 (0) ; 0 (0) ; 0 (0) ; |hh ;
; |CNT10:C0| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |hh|CNT10:C0 ;
; |CNT10:C1| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |hh|CNT10:C1 ;
; |CNT10:C2| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |hh|CNT10:C2 ;
; |CNT10:C3| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |hh|CNT10:C3 ;
; |REG4:R1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |hh|REG4:R1 ;
; |REG4:R2| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |hh|REG4:R2 ;
; |REG4:R3| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |hh|REG4:R3 ;
; |REG4:R4| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |hh|REG4:R4 ;
; |SM:SM1| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |hh|SM:SM1 ;
; |SM:SM2| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |hh|SM:SM2 ;
; |SM:SM3| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |hh|SM:SM3 ;
; |SM:SM4| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |hh|SM:SM4 ;
; |TESTFRE:T| ; 2 (2) ; 1 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |hh|TESTFRE:T ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 36 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 19 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 15 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/临时/EDA/课程设计/hh/hh.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Thu Jun 21 16:05:38 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hh -c hh
Info: Found 2 design units, including 1 entities, in source file hh.vhd
Info: Found design unit 1: hh-ONE
Info: Found entity 1: hh
Info: Elaborating entity "hh" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at hh.vhd(43): object "OUTX4" assigned a value but never read
Warning: Using design file TESTFRE.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: TESTFRE-ONE
Info: Found entity 1: TESTFRE
Info: Elaborating entity "TESTFRE" for hierarchy "TESTFRE:T"
Warning: Using design file CNT10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: CNT10-ONE
Info: Found entity 1: CNT10
Info: Elaborating entity "CNT10" for hierarchy "CNT10:C0"
Warning (10492): VHDL Process Statement warning at CNT10.vhd(24): signal "SS" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file REG4.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: REG4-ONE
Info: Found entity 1: REG4
Info: Elaborating entity "REG4" for hierarchy "REG4:R1"
Warning: Using design file SM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: SM-ONE
Info: Found entity 1: SM
Info: Elaborating entity "SM" for hierarchy "SM:SM1"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "LED0[0]" stuck at GND
Warning: Pin "LED1[0]" stuck at GND
Warning: Pin "LED2[0]" stuck at GND
Warning: Pin "LED3[0]" stuck at GND
Info: Implemented 99 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 32 output pins
Info: Implemented 65 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
Info: Processing ended: Thu Jun 21 16:05:42 2007
Info: Elapsed time: 00:00:04
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