testfre.tan.qmsg

用VHDL 语言描述频率计的设计

{ "Info" "ITDB_FULL_TCO_RESULT" "CLKK RSTC div2clk 11.916 ns register " "Info: tco from clock \"CLKK\" to destination pin \"RSTC\" through register \"div2clk\" is 11.916 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKK source 6.795 ns + Longest register " "Info: + Longest clock path from clock \"CLKK\" to source register is 6.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKK 1 CLK PIN_11 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'CLKK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "" { CLKK } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.615 ns) + CELL(0.711 ns) 6.795 ns div2clk 2 REG LC_X1_Y9_N2 4 " "Info: 2: + IC(4.615 ns) + CELL(0.711 ns) = 6.795 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "5.326 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 32.08 % ) " "Info: Total cell delay = 2.180 ns ( 32.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 67.92 % ) " "Info: Total interconnect delay = 4.615 ns ( 67.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "6.795 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.795 ns" { CLKK CLKK~out0 div2clk } { 0.000ns 0.000ns 4.615ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.897 ns + Longest register pin " "Info: + Longest register to pin delay is 4.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div2clk 1 REG LC_X1_Y9_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "" { div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.292 ns) 0.845 ns process1~0 2 COMB LC_X1_Y9_N5 1 " "Info: 2: + IC(0.553 ns) + CELL(0.292 ns) = 0.845 ns; Loc. = LC_X1_Y9_N5; Fanout = 1; COMB Node = 'process1~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "0.845 ns" { div2clk process1~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.928 ns) + CELL(2.124 ns) 4.897 ns RSTC 3 PIN PIN_27 0 " "Info: 3: + IC(1.928 ns) + CELL(2.124 ns) = 4.897 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'RSTC'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "4.052 ns" { process1~0 RSTC } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.416 ns ( 49.34 % ) " "Info: Total cell delay = 2.416 ns ( 49.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.481 ns ( 50.66 % ) " "Info: Total interconnect delay = 2.481 ns ( 50.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "4.897 ns" { div2clk process1~0 RSTC } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.897 ns" { div2clk process1~0 RSTC } { 0.000ns 0.553ns 1.928ns } { 0.000ns 0.292ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "6.795 ns" { CLKK div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.795 ns" { CLKK CLKK~out0 div2clk } { 0.000ns 0.000ns 4.615ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "4.897 ns" { div2clk process1~0 RSTC } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.897 ns" { div2clk process1~0 RSTC } { 0.000ns 0.553ns 1.928ns } { 0.000ns 0.292ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLKK RSTC 10.512 ns Longest " "Info: Longest tpd from source pin \"CLKK\" to destination pin \"RSTC\" is 10.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKK 1 CLK PIN_11 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'CLKK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "" { CLKK } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.549 ns) + CELL(0.442 ns) 6.460 ns process1~0 2 COMB LC_X1_Y9_N5 1 " "Info: 2: + IC(4.549 ns) + CELL(0.442 ns) = 6.460 ns; Loc. = LC_X1_Y9_N5; Fanout = 1; COMB Node = 'process1~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "4.991 ns" { CLKK process1~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.928 ns) + CELL(2.124 ns) 10.512 ns RSTC 3 PIN PIN_27 0 " "Info: 3: + IC(1.928 ns) + CELL(2.124 ns) = 10.512 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'RSTC'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "4.052 ns" { process1~0 RSTC } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/频控模块/TESTFRE.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.035 ns ( 38.38 % ) " "Info: Total cell delay = 4.035 ns ( 38.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.477 ns ( 61.62 % ) " "Info: Total interconnect delay = 6.477 ns ( 61.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "TESTFRE" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/频控模块/db/TESTFRE.quartus_db" { Floorplan "F:/临时/EDA/课程设计/频控模块/" "" "10.512 ns" { CLKK process1~0 RSTC } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.512 ns" { CLKK CLKK~out0 process1~0 RSTC } { 0.000ns 0.000ns 4.549ns 1.928ns } { 0.000ns 1.469ns 0.442ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 14 20:38:40 2007 " "Info: Processing ended: Thu Jun 14 20:38:40 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}