hh.fit.qmsg

用VHDL 语言描述频率计的设计

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED0\[0\] GND " "Info: Pin LED0\[0\] has GND driving its datain port" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED0\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { LED0[0] } "NODE_NAME" } "" } } { "F:/临时/EDA/课程设计/hh/hh.fld" "" { Floorplan "F:/临时/EDA/课程设计/hh/hh.fld" "" "" { LED0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED1\[0\] GND " "Info: Pin LED1\[0\] has GND driving its datain port" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 8 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED1\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { LED1[0] } "NODE_NAME" } "" } } { "F:/临时/EDA/课程设计/hh/hh.fld" "" { Floorplan "F:/临时/EDA/课程设计/hh/hh.fld" "" "" { LED1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED2\[0\] GND " "Info: Pin LED2\[0\] has GND driving its datain port" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED2\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { LED2[0] } "NODE_NAME" } "" } } { "F:/临时/EDA/课程设计/hh/hh.fld" "" { Floorplan "F:/临时/EDA/课程设计/hh/hh.fld" "" "" { LED2[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED3\[0\] GND " "Info: Pin LED3\[0\] has GND driving its datain port" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED3\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { LED3[0] } "NODE_NAME" } "" } } { "F:/临时/EDA/课程设计/hh/hh.fld" "" { Floorplan "F:/临时/EDA/课程设计/hh/hh.fld" "" "" { LED3[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 21 16:05:50 2007 " "Info: Processing ended: Thu Jun 21 16:05:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}