cnt10.tan.qmsg

用VHDL 语言描述频率计的设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register SS\[1\] SS\[3\] 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"SS\[1\]\" and destination register \"SS\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.303 ns + Longest register register " "Info: + Longest register to register delay is 1.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SS\[1\] 1 REG LC_X10_Y13_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y13_N6; Fanout = 5; REG Node = 'SS\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { SS[1] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.738 ns) 1.303 ns SS\[3\] 2 REG LC_X10_Y13_N2 4 " "Info: 2: + IC(0.565 ns) + CELL(0.738 ns) = 1.303 ns; Loc. = LC_X10_Y13_N2; Fanout = 4; REG Node = 'SS\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "1.303 ns" { SS[1] SS[3] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 56.64 % ) " "Info: Total cell delay = 0.738 ns ( 56.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.565 ns ( 43.36 % ) " "Info: Total interconnect delay = 0.565 ns ( 43.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "1.303 ns" { SS[1] SS[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.303 ns" { SS[1] SS[3] } { 0.000ns 0.565ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns SS\[3\] 2 REG LC_X10_Y13_N2 4 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N2; Fanout = 4; REG Node = 'SS\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "1.298 ns" { CLK SS[3] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[3] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.767 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns SS\[1\] 2 REG LC_X10_Y13_N6 5 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N6; Fanout = 5; REG Node = 'SS\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "1.298 ns" { CLK SS[1] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[3] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "1.303 ns" { SS[1] SS[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.303 ns" { SS[1] SS[3] } { 0.000ns 0.565ns } { 0.000ns 0.738ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[3] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { SS[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { SS[3] } {  } {  } } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "SS\[0\] EN CLK 4.684 ns register " "Info: tsu for register \"SS\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 4.684 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.414 ns + Longest pin register " "Info: + Longest pin to register delay is 7.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns EN 1 PIN PIN_131 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_131; Fanout = 5; PIN Node = 'EN'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { EN } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.072 ns) + CELL(0.867 ns) 7.414 ns SS\[0\] 2 REG LC_X10_Y13_N0 6 " "Info: 2: + IC(5.072 ns) + CELL(0.867 ns) = 7.414 ns; Loc. = LC_X10_Y13_N0; Fanout = 6; REG Node = 'SS\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "5.939 ns" { EN SS[0] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns ( 31.59 % ) " "Info: Total cell delay = 2.342 ns ( 31.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.072 ns ( 68.41 % ) " "Info: Total interconnect delay = 5.072 ns ( 68.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "7.414 ns" { EN SS[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.414 ns" { EN EN~out0 SS[0] } { 0.000ns 0.000ns 5.072ns } { 0.000ns 1.475ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns SS\[0\] 2 REG LC_X10_Y13_N0 6 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N0; Fanout = 6; REG Node = 'SS\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "1.298 ns" { CLK SS[0] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[0] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "7.414 ns" { EN SS[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.414 ns" { EN EN~out0 SS[0] } { 0.000ns 0.000ns 5.072ns } { 0.000ns 1.475ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[0] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK OUTX\[2\] SS\[2\] 7.193 ns register " "Info: tco from clock \"CLK\" to destination pin \"OUTX\[2\]\" through register \"SS\[2\]\" is 7.193 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.767 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns SS\[2\] 2 REG LC_X10_Y13_N5 5 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N5; Fanout = 5; REG Node = 'SS\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "1.298 ns" { CLK SS[2] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.202 ns + Longest register pin " "Info: + Longest register to pin delay is 4.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SS\[2\] 1 REG LC_X10_Y13_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y13_N5; Fanout = 5; REG Node = 'SS\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { SS[2] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.078 ns) + CELL(2.124 ns) 4.202 ns OUTX\[2\] 2 PIN PIN_2 0 " "Info: 2: + IC(2.078 ns) + CELL(2.124 ns) = 4.202 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'OUTX\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "4.202 ns" { SS[2] OUTX[2] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 50.55 % ) " "Info: Total cell delay = 2.124 ns ( 50.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.078 ns ( 49.45 % ) " "Info: Total interconnect delay = 2.078 ns ( 49.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "4.202 ns" { SS[2] OUTX[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.202 ns" { SS[2] OUTX[2] } { 0.000ns 2.078ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "4.202 ns" { SS[2] OUTX[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.202 ns" { SS[2] OUTX[2] } { 0.000ns 2.078ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "SS\[2\] EN CLK -4.214 ns register " "Info: th for register \"SS\[2\]\" (data pin = \"EN\", clock pin = \"CLK\") is -4.214 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns SS\[2\] 2 REG LC_X10_Y13_N5 5 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N5; Fanout = 5; REG Node = 'SS\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "1.298 ns" { CLK SS[2] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.996 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.996 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns EN 1 PIN PIN_131 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_131; Fanout = 5; PIN Node = 'EN'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "" { EN } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.043 ns) + CELL(0.478 ns) 6.996 ns SS\[2\] 2 REG LC_X10_Y13_N5 5 " "Info: 2: + IC(5.043 ns) + CELL(0.478 ns) = 6.996 ns; Loc. = LC_X10_Y13_N5; Fanout = 5; REG Node = 'SS\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "5.521 ns" { EN SS[2] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/十进制加法器/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns ( 27.92 % ) " "Info: Total cell delay = 1.953 ns ( 27.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.043 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.043 ns ( 72.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "6.996 ns" { EN SS[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.996 ns" { EN EN~out0 SS[2] } { 0.000ns 0.000ns 5.043ns } { 0.000ns 1.475ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "2.767 ns" { CLK SS[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 SS[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CNT10" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/十进制加法器/db/CNT10.quartus_db" { Floorplan "F:/临时/EDA/课程设计/十进制加法器/" "" "6.996 ns" { EN SS[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.996 ns" { EN EN~out0 SS[2] } { 0.000ns 0.000ns 5.043ns } { 0.000ns 1.475ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}