hh.tan.qmsg

用VHDL 语言描述频率计的设计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CNT10:C2\|OUTY " "Info: Detected ripple clock \"CNT10:C2\|OUTY\" as buffer" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CNT10:C2\|OUTY" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT10:C1\|OUTY " "Info: Detected ripple clock \"CNT10:C1\|OUTY\" as buffer" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CNT10:C1\|OUTY" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT10:C0\|OUTY " "Info: Detected ripple clock \"CNT10:C0\|OUTY\" as buffer" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CNT10:C0\|OUTY" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "TESTFRE:T\|div2clk " "Info: Detected ripple clock \"TESTFRE:T\|div2clk\" as buffer" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TESTFRE:T\|div2clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK1 register register TESTFRE:T\|div2clk TESTFRE:T\|div2clk 275.03 MHz Internal " "Info: Clock \"CLK1\" Internal fmax is restricted to 275.03 MHz between source register \"TESTFRE:T\|div2clk\" and destination register \"TESTFRE:T\|div2clk\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.027 ns + Longest register register " "Info: + Longest register to register delay is 1.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TESTFRE:T\|div2clk 1 REG LC_X10_Y6_N2 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T\|div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.549 ns) + CELL(0.478 ns) 1.027 ns TESTFRE:T\|div2clk 2 REG LC_X10_Y6_N2 37 " "Info: 2: + IC(0.549 ns) + CELL(0.478 ns) = 1.027 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T\|div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.027 ns" { TESTFRE:T|div2clk TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 46.54 % ) " "Info: Total cell delay = 0.478 ns ( 46.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.549 ns ( 53.46 % ) " "Info: Total interconnect delay = 0.549 ns ( 53.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.027 ns" { TESTFRE:T|div2clk TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.027 ns" { TESTFRE:T|div2clk TESTFRE:T|div2clk } { 0.000ns 0.549ns } { 0.000ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 destination 7.750 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK1\" to destination register is 7.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK1 1 CLK PIN_130 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_130; Fanout = 2; CLK Node = 'CLK1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { CLK1 } "NODE_NAME" } "" } } { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.564 ns) + CELL(0.711 ns) 7.750 ns TESTFRE:T\|div2clk 2 REG LC_X10_Y6_N2 37 " "Info: 2: + IC(5.564 ns) + CELL(0.711 ns) = 7.750 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T\|div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "6.275 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 28.21 % ) " "Info: Total cell delay = 2.186 ns ( 28.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.564 ns ( 71.79 % ) " "Info: Total interconnect delay = 5.564 ns ( 71.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "7.750 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.750 ns" { CLK1 CLK1~out0 TESTFRE:T|div2clk } { 0.000ns 0.000ns 5.564ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 source 7.750 ns - Longest register " "Info: - Longest clock path from clock \"CLK1\" to source register is 7.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK1 1 CLK PIN_130 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_130; Fanout = 2; CLK Node = 'CLK1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { CLK1 } "NODE_NAME" } "" } } { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.564 ns) + CELL(0.711 ns) 7.750 ns TESTFRE:T\|div2clk 2 REG LC_X10_Y6_N2 37 " "Info: 2: + IC(5.564 ns) + CELL(0.711 ns) = 7.750 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T\|div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "6.275 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 28.21 % ) " "Info: Total cell delay = 2.186 ns ( 28.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.564 ns ( 71.79 % ) " "Info: Total interconnect delay = 5.564 ns ( 71.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "7.750 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.750 ns" { CLK1 CLK1~out0 TESTFRE:T|div2clk } { 0.000ns 0.000ns 5.564ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "7.750 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.750 ns" { CLK1 CLK1~out0 TESTFRE:T|div2clk } { 0.000ns 0.000ns 5.564ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "7.750 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.750 ns" { CLK1 CLK1~out0 TESTFRE:T|div2clk } { 0.000ns 0.000ns 5.564ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.027 ns" { TESTFRE:T|div2clk TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.027 ns" { TESTFRE:T|div2clk TESTFRE:T|div2clk } { 0.000ns 0.549ns } { 0.000ns 0.478ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "7.750 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.750 ns" { CLK1 CLK1~out0 TESTFRE:T|div2clk } { 0.000ns 0.000ns 5.564ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "7.750 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.750 ns" { CLK1 CLK1~out0 TESTFRE:T|div2clk } { 0.000ns 0.000ns 5.564ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { TESTFRE:T|div2clk } {  } {  } } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "UCLK register register CNT10:C2\|SS\[0\] CNT10:C2\|SS\[1\] 275.03 MHz Internal " "Info: Clock \"UCLK\" Internal fmax is restricted to 275.03 MHz between source register \"CNT10:C2\|SS\[0\]\" and destination register \"CNT10:C2\|SS\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.319 ns + Longest register register " "Info: + Longest register to register delay is 1.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT10:C2\|SS\[0\] 1 REG LC_X26_Y6_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y6_N2; Fanout = 6; REG Node = 'CNT10:C2\|SS\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { CNT10:C2|SS[0] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.581 ns) + CELL(0.738 ns) 1.319 ns CNT10:C2\|SS\[1\] 2 REG LC_X26_Y6_N5 5 " "Info: 2: + IC(0.581 ns) + CELL(0.738 ns) = 1.319 ns; Loc. = LC_X26_Y6_N5; Fanout = 5; REG Node = 'CNT10:C2\|SS\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.319 ns" { CNT10:C2|SS[0] CNT10:C2|SS[1] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 55.95 % ) " "Info: Total cell delay = 0.738 ns ( 55.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.581 ns ( 44.05 % ) " "Info: Total interconnect delay = 0.581 ns ( 44.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.319 ns" { CNT10:C2|SS[0] CNT10:C2|SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.319 ns" { CNT10:C2|SS[0] CNT10:C2|SS[1] } { 0.000ns 0.581ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "UCLK destination 12.081 ns + Shortest register " "Info: + Shortest clock path from clock \"UCLK\" to destination register is 12.081 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns UCLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'UCLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { UCLK } "NODE_NAME" } "" } } { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns CNT10:C0\|OUTY 2 REG LC_X8_Y6_N5 5 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N5; Fanout = 5; REG Node = 'CNT10:C0\|OUTY'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.493 ns" { UCLK CNT10:C0|OUTY } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.502 ns) + CELL(0.935 ns) 7.399 ns CNT10:C1\|OUTY 3 REG LC_X25_Y6_N4 5 " "Info: 3: + IC(3.502 ns) + CELL(0.935 ns) = 7.399 ns; Loc. = LC_X25_Y6_N4; Fanout = 5; REG Node = 'CNT10:C1\|OUTY'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "4.437 ns" { CNT10:C0|OUTY CNT10:C1|OUTY } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.971 ns) + CELL(0.711 ns) 12.081 ns CNT10:C2\|SS\[1\] 4 REG LC_X26_Y6_N5 5 " "Info: 4: + IC(3.971 ns) + CELL(0.711 ns) = 12.081 ns; Loc. = LC_X26_Y6_N5; Fanout = 5; REG Node = 'CNT10:C2\|SS\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "4.682 ns" { CNT10:C1|OUTY CNT10:C2|SS[1] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.52 % ) " "Info: Total cell delay = 4.050 ns ( 33.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.031 ns ( 66.48 % ) " "Info: Total interconnect delay = 8.031 ns ( 66.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "12.081 ns" { UCLK CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.081 ns" { UCLK UCLK~out0 CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[1] } { 0.000ns 0.000ns 0.558ns 3.502ns 3.971ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "UCLK source 12.081 ns - Longest register " "Info: - Longest clock path from clock \"UCLK\" to source register is 12.081 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns UCLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'UCLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { UCLK } "NODE_NAME" } "" } } { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns CNT10:C0\|OUTY 2 REG LC_X8_Y6_N5 5 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N5; Fanout = 5; REG Node = 'CNT10:C0\|OUTY'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.493 ns" { UCLK CNT10:C0|OUTY } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.502 ns) + CELL(0.935 ns) 7.399 ns CNT10:C1\|OUTY 3 REG LC_X25_Y6_N4 5 " "Info: 3: + IC(3.502 ns) + CELL(0.935 ns) = 7.399 ns; Loc. = LC_X25_Y6_N4; Fanout = 5; REG Node = 'CNT10:C1\|OUTY'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "4.437 ns" { CNT10:C0|OUTY CNT10:C1|OUTY } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.971 ns) + CELL(0.711 ns) 12.081 ns CNT10:C2\|SS\[0\] 4 REG LC_X26_Y6_N2 6 " "Info: 4: + IC(3.971 ns) + CELL(0.711 ns) = 12.081 ns; Loc. = LC_X26_Y6_N2; Fanout = 6; REG Node = 'CNT10:C2\|SS\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "4.682 ns" { CNT10:C1|OUTY CNT10:C2|SS[0] } "NODE_NAME" } "" } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.52 % ) " "Info: Total cell delay = 4.050 ns ( 33.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.031 ns ( 66.48 % ) " "Info: Total interconnect delay = 8.031 ns ( 66.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "12.081 ns" { UCLK CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.081 ns" { UCLK UCLK~out0 CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[0] } { 0.000ns 0.000ns 0.558ns 3.502ns 3.971ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "12.081 ns" { UCLK CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.081 ns" { UCLK UCLK~out0 CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[1] } { 0.000ns 0.000ns 0.558ns 3.502ns 3.971ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "12.081 ns" { UCLK CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.081 ns" { UCLK UCLK~out0 CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[0] } { 0.000ns 0.000ns 0.558ns 3.502ns 3.971ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.319 ns" { CNT10:C2|SS[0] CNT10:C2|SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.319 ns" { CNT10:C2|SS[0] CNT10:C2|SS[1] } { 0.000ns 0.581ns } { 0.000ns 0.738ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "12.081 ns" { UCLK CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.081 ns" { UCLK UCLK~out0 CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[1] } { 0.000ns 0.000ns 0.558ns 3.502ns 3.971ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "12.081 ns" { UCLK CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.081 ns" { UCLK UCLK~out0 CNT10:C0|OUTY CNT10:C1|OUTY CNT10:C2|SS[0] } { 0.000ns 0.000ns 0.558ns 3.502ns 3.971ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { CNT10:C2|SS[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { CNT10:C2|SS[1] } {  } {  } } } { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK1 LED0\[2\] REG4:R1\|DOUT\[3\] 18.829 ns register " "Info: tco from clock \"CLK1\" to destination pin \"LED0\[2\]\" through register \"REG4:R1\|DOUT\[3\]\" is 18.829 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 source 12.531 ns + Longest register " "Info: + Longest clock path from clock \"CLK1\" to source register is 12.531 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK1 1 CLK PIN_130 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_130; Fanout = 2; CLK Node = 'CLK1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { CLK1 } "NODE_NAME" } "" } } { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.564 ns) + CELL(0.935 ns) 7.974 ns TESTFRE:T\|div2clk 2 REG LC_X10_Y6_N2 37 " "Info: 2: + IC(5.564 ns) + CELL(0.935 ns) = 7.974 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T\|div2clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "6.499 ns" { CLK1 TESTFRE:T|div2clk } "NODE_NAME" } "" } } { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.846 ns) + CELL(0.711 ns) 12.531 ns REG4:R1\|DOUT\[3\] 3 REG LC_X8_Y5_N5 7 " "Info: 3: + IC(3.846 ns) + CELL(0.711 ns) = 12.531 ns; Loc. = LC_X8_Y5_N5; Fanout = 7; REG Node = 'REG4:R1\|DOUT\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "4.557 ns" { TESTFRE:T|div2clk REG4:R1|DOUT[3] } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/hh/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 24.91 % ) " "Info: Total cell delay = 3.121 ns ( 24.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.410 ns ( 75.09 % ) " "Info: Total interconnect delay = 9.410 ns ( 75.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "12.531 ns" { CLK1 TESTFRE:T|div2clk REG4:R1|DOUT[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.531 ns" { CLK1 CLK1~out0 TESTFRE:T|div2clk REG4:R1|DOUT[3] } { 0.000ns 0.000ns 5.564ns 3.846ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/hh/REG4.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.074 ns + Longest register pin " "Info: + Longest register to pin delay is 6.074 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG4:R1\|DOUT\[3\] 1 REG LC_X8_Y5_N5 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y5_N5; Fanout = 7; REG Node = 'REG4:R1\|DOUT\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "" { REG4:R1|DOUT[3] } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/hh/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.590 ns) 1.350 ns SM:SM1\|O\[2\]~213 2 COMB LC_X8_Y5_N9 1 " "Info: 2: + IC(0.760 ns) + CELL(0.590 ns) = 1.350 ns; Loc. = LC_X8_Y5_N9; Fanout = 1; COMB Node = 'SM:SM1\|O\[2\]~213'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "1.350 ns" { REG4:R1|DOUT[3] SM:SM1|O[2]~213 } "NODE_NAME" } "" } } { "SM.vhd" "" { Text "F:/临时/EDA/课程设计/hh/SM.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.616 ns) + CELL(2.108 ns) 6.074 ns LED0\[2\] 3 PIN PIN_57 0 " "Info: 3: + IC(2.616 ns) + CELL(2.108 ns) = 6.074 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'LED0\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "4.724 ns" { SM:SM1|O[2]~213 LED0[2] } "NODE_NAME" } "" } } { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns ( 44.42 % ) " "Info: Total cell delay = 2.698 ns ( 44.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.376 ns ( 55.58 % ) " "Info: Total interconnect delay = 3.376 ns ( 55.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "6.074 ns" { REG4:R1|DOUT[3] SM:SM1|O[2]~213 LED0[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.074 ns" { REG4:R1|DOUT[3] SM:SM1|O[2]~213 LED0[2] } { 0.000ns 0.760ns 2.616ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "12.531 ns" { CLK1 TESTFRE:T|div2clk REG4:R1|DOUT[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.531 ns" { CLK1 CLK1~out0 TESTFRE:T|div2clk REG4:R1|DOUT[3] } { 0.000ns 0.000ns 5.564ns 3.846ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "hh" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/hh/db/hh.quartus_db" { Floorplan "F:/临时/EDA/课程设计/hh/" "" "6.074 ns" { REG4:R1|DOUT[3] SM:SM1|O[2]~213 LED0[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.074 ns" { REG4:R1|DOUT[3] SM:SM1|O[2]~213 LED0[2] } { 0.000ns 0.760ns 2.616ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}