sm.hier_info

用VHDL 语言描述频率计的设计

|SM
I[0] => Mux~0.IN19
I[0] => Mux~1.IN19
I[0] => Mux~2.IN19
I[0] => Mux~3.IN19
I[0] => Mux~4.IN19
I[0] => Mux~5.IN19
I[0] => Mux~6.IN19
I[1] => Mux~0.IN18
I[1] => Mux~1.IN18
I[1] => Mux~2.IN18
I[1] => Mux~3.IN18
I[1] => Mux~4.IN18
I[1] => Mux~5.IN18
I[1] => Mux~6.IN18
I[2] => Mux~0.IN17
I[2] => Mux~1.IN17
I[2] => Mux~2.IN17
I[2] => Mux~3.IN17
I[2] => Mux~4.IN17
I[2] => Mux~5.IN17
I[2] => Mux~6.IN17
I[3] => Mux~0.IN16
I[3] => Mux~1.IN16
I[3] => Mux~2.IN16
I[3] => Mux~3.IN16
I[3] => Mux~4.IN16
I[3] => Mux~5.IN16
I[3] => Mux~6.IN16
O[0] <= <GND>
O[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
O[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
O[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
O[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
O[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
O[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
O[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE