📄 testfre.tan.rpt
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Timing Analyzer report for TESTFRE
Thu Jun 14 20:38:40 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLKK'
6. tco
7. tpd
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 11.916 ns ; div2clk ; RSTC ; CLKK ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 10.512 ns ; CLKK ; RSTC ; -- ; -- ; 0 ;
; Clock Setup: 'CLKK' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; div2clk ; div2clk ; CLKK ; CLKK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLKK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLKK' ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; div2clk ; div2clk ; CLKK ; CLKK ; None ; None ; 1.026 ns ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------+-------+------------+
; N/A ; None ; 11.916 ns ; div2clk ; RSTC ; CLKK ;
; N/A ; None ; 11.389 ns ; div2clk ; LOADC ; CLKK ;
; N/A ; None ; 10.940 ns ; div2clk ; ENC ; CLKK ;
+-------+--------------+------------+---------+-------+------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 10.512 ns ; CLKK ; RSTC ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Thu Jun 14 20:38:39 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off TESTFRE -c TESTFRE --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLKK" is an undefined clock
Info: Clock "CLKK" Internal fmax is restricted to 275.03 MHz between source register "div2clk" and destination register "div2clk"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.026 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'
Info: 2: + IC(0.548 ns) + CELL(0.478 ns) = 1.026 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'
Info: Total cell delay = 0.478 ns ( 46.59 % )
Info: Total interconnect delay = 0.548 ns ( 53.41 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLKK" to destination register is 6.795 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'CLKK'
Info: 2: + IC(4.615 ns) + CELL(0.711 ns) = 6.795 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'
Info: Total cell delay = 2.180 ns ( 32.08 % )
Info: Total interconnect delay = 4.615 ns ( 67.92 % )
Info: - Longest clock path from clock "CLKK" to source register is 6.795 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'CLKK'
Info: 2: + IC(4.615 ns) + CELL(0.711 ns) = 6.795 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'
Info: Total cell delay = 2.180 ns ( 32.08 % )
Info: Total interconnect delay = 4.615 ns ( 67.92 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLKK" to destination pin "RSTC" through register "div2clk" is 11.916 ns
Info: + Longest clock path from clock "CLKK" to source register is 6.795 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'CLKK'
Info: 2: + IC(4.615 ns) + CELL(0.711 ns) = 6.795 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'
Info: Total cell delay = 2.180 ns ( 32.08 % )
Info: Total interconnect delay = 4.615 ns ( 67.92 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 4.897 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y9_N2; Fanout = 4; REG Node = 'div2clk'
Info: 2: + IC(0.553 ns) + CELL(0.292 ns) = 0.845 ns; Loc. = LC_X1_Y9_N5; Fanout = 1; COMB Node = 'process1~0'
Info: 3: + IC(1.928 ns) + CELL(2.124 ns) = 4.897 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'RSTC'
Info: Total cell delay = 2.416 ns ( 49.34 % )
Info: Total interconnect delay = 2.481 ns ( 50.66 % )
Info: Longest tpd from source pin "CLKK" to destination pin "RSTC" is 10.512 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'CLKK'
Info: 2: + IC(4.549 ns) + CELL(0.442 ns) = 6.460 ns; Loc. = LC_X1_Y9_N5; Fanout = 1; COMB Node = 'process1~0'
Info: 3: + IC(1.928 ns) + CELL(2.124 ns) = 10.512 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'RSTC'
Info: Total cell delay = 4.035 ns ( 38.38 % )
Info: Total interconnect delay = 6.477 ns ( 61.62 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Jun 14 20:38:40 2007
Info: Elapsed time: 00:00:01
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