hh.vhd

用VHDL 语言描述频率计的设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY hh IS
   PORT(CLK1:IN STD_LOGIC;
        UCLK:IN STD_LOGIC;
        LED0:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        LED1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        LED2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        LED3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;

ARCHITECTURE ONE OF hh IS 
   COMPONENT CNT10 IS
      PORT(CLK:IN STD_LOGIC;
           RST:IN STD_LOGIC;
           EN:IN STD_LOGIC;
           OUTX:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           OUTY:OUT STD_LOGIC);
   END COMPONENT;
   
   COMPONENT REG4 IS
      PORT(LOAD:IN STD_LOGIC;
           DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
   END COMPONENT;
   
   COMPONENT TESTFRE IS
      PORT(CLKK:IN STD_LOGIC;
           ENC:OUT STD_LOGIC;
           RSTC:OUT STD_LOGIC;
           LOADC:OUT STD_LOGIC);
   END COMPONENT;

   COMPONENT SM IS
     PORT(I:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
   END COMPONENT;
   
   SIGNAL E:STD_LOGIC;
   SIGNAL R:STD_LOGIC;
   SIGNAL L:STD_LOGIC;                                      
   SIGNAL OUTX0,OUTX1,OUTX2,OUTX3,OUTX4:STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL OUTY0,OUTY1,OUTY2,OUTY3:STD_LOGIC;
   SIGNAL I1,I2,I3,I4:STD_LOGIC_VECTOR(3 DOWNTO 0);
   
BEGIN               
 T: TESTFRE PORT MAP(
    CLKK=>CLK1,
    ENC=>E,
    RSTC=>R,
    LOADC=>L);

 C0:CNT10 PORT MAP(
   CLK=>UCLK,
   RST=>R,
   EN=>E,
   OUTX=>OUTX0,
   OUTY=>OUTY0);
 C1:CNT10 PORT MAP(
   CLK=>OUTY0,
   RST=>R,
   EN=>E,
   OUTX=>OUTX1,
   OUTY=>OUTY1);
 C2:CNT10 PORT MAP(
   CLK=>OUTY1,
   RST=>R,
   EN=>E,
   OUTX=>OUTX2,
   OUTY=>OUTY2);
 C3:CNT10 PORT MAP(
   CLK=>OUTY2,
   RST=>R,
   EN=>E,
   OUTX=>OUTX3,
   OUTY=>OUTY3);
 C4:CNT10 PORT MAP(
   CLK=>OUTY3,
   RST=>R,
   EN=>E,
   OUTX=>OUTX4);

 R1:REG4 PORT MAP(
   LOAD=>L,
   DIN=>OUTX0,
   DOUT=>I1);  
 R2:REG4 PORT MAP(
   LOAD=>L,
   DIN=>OUTX1,
   DOUT=>I2); 
 R3:REG4 PORT MAP(
   LOAD=>L,
   DIN=>OUTX2,
   DOUT=>I3); 
 R4:REG4 PORT MAP(
   LOAD=>L,
   DIN=>OUTX3,
   DOUT=>I4); 

 SM1:SM PORT MAP(
   I=>I1,
   O=>LED0);
 SM2:SM PORT MAP(
   I=>I2,
   O=>LED1); 
 SM3:SM PORT MAP(
   I=>I3,
   O=>LED2); 
 SM4:SM PORT MAP(
   I=>I4,
   O=>LED3);
 END ONE;