reg4.map.eqn

用VHDL 语言描述频率计的设计

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--A1L8Q is DOUT[0]~reg0
--operation mode is normal

A1L8Q_lut_out = DIN[0];
A1L8Q = DFFEAS(A1L8Q_lut_out, LOAD, VCC, , , , , , );


--A1L10Q is DOUT[1]~reg0
--operation mode is normal

A1L10Q_lut_out = DIN[1];
A1L10Q = DFFEAS(A1L10Q_lut_out, LOAD, VCC, , , , , , );


--A1L12Q is DOUT[2]~reg0
--operation mode is normal

A1L12Q_lut_out = DIN[2];
A1L12Q = DFFEAS(A1L12Q_lut_out, LOAD, VCC, , , , , , );


--A1L14Q is DOUT[3]~reg0
--operation mode is normal

A1L14Q_lut_out = DIN[3];
A1L14Q = DFFEAS(A1L14Q_lut_out, LOAD, VCC, , , , , , );


--DIN[0] is DIN[0]
--operation mode is input

DIN[0] = INPUT();


--LOAD is LOAD
--operation mode is input

LOAD = INPUT();


--DIN[1] is DIN[1]
--operation mode is input

DIN[1] = INPUT();


--DIN[2] is DIN[2]
--operation mode is input

DIN[2] = INPUT();


--DIN[3] is DIN[3]
--operation mode is input

DIN[3] = INPUT();


--DOUT[0] is DOUT[0]
--operation mode is output

DOUT[0] = OUTPUT(A1L8Q);


--DOUT[1] is DOUT[1]
--operation mode is output

DOUT[1] = OUTPUT(A1L10Q);


--DOUT[2] is DOUT[2]
--operation mode is output

DOUT[2] = OUTPUT(A1L12Q);


--DOUT[3] is DOUT[3]
--operation mode is output

DOUT[3] = OUTPUT(A1L14Q);