📄 reg4.tan.rpt
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Timing Analyzer report for REG4
Tue Jun 12 15:34:44 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------------+--------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------------+--------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.043 ns ; DIN[2] ; DOUT[2]~reg0 ; -- ; LOAD ; 0 ;
; Worst-case tco ; N/A ; None ; 6.775 ns ; DOUT[1]~reg0 ; DOUT[1] ; LOAD ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -3.359 ns ; DIN[1] ; DOUT[1]~reg0 ; -- ; LOAD ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------------+--------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; LOAD ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+--------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+--------+--------------+----------+
; N/A ; None ; 4.043 ns ; DIN[2] ; DOUT[2]~reg0 ; LOAD ;
; N/A ; None ; 3.821 ns ; DIN[0] ; DOUT[0]~reg0 ; LOAD ;
; N/A ; None ; 3.425 ns ; DIN[3] ; DOUT[3]~reg0 ; LOAD ;
; N/A ; None ; 3.411 ns ; DIN[1] ; DOUT[1]~reg0 ; LOAD ;
+-------+--------------+------------+--------+--------------+----------+
+-------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A ; None ; 6.775 ns ; DOUT[1]~reg0 ; DOUT[1] ; LOAD ;
; N/A ; None ; 6.410 ns ; DOUT[2]~reg0 ; DOUT[2] ; LOAD ;
; N/A ; None ; 6.393 ns ; DOUT[0]~reg0 ; DOUT[0] ; LOAD ;
; N/A ; None ; 6.259 ns ; DOUT[3]~reg0 ; DOUT[3] ; LOAD ;
+-------+--------------+------------+--------------+---------+------------+
+----------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+--------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+--------+--------------+----------+
; N/A ; None ; -3.359 ns ; DIN[1] ; DOUT[1]~reg0 ; LOAD ;
; N/A ; None ; -3.373 ns ; DIN[3] ; DOUT[3]~reg0 ; LOAD ;
; N/A ; None ; -3.769 ns ; DIN[0] ; DOUT[0]~reg0 ; LOAD ;
; N/A ; None ; -3.991 ns ; DIN[2] ; DOUT[2]~reg0 ; LOAD ;
+---------------+-------------+-----------+--------+--------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Tue Jun 12 15:34:43 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off REG4 -c REG4 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "LOAD" is an undefined clock
Info: No valid register-to-register data paths exist for clock "LOAD"
Info: tsu for register "DOUT[2]~reg0" (data pin = "DIN[2]", clock pin = "LOAD") is 4.043 ns
Info: + Longest pin to register delay is 6.787 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_121; Fanout = 1; PIN Node = 'DIN[2]'
Info: 2: + IC(5.003 ns) + CELL(0.309 ns) = 6.787 ns; Loc. = LC_X20_Y13_N2; Fanout = 1; REG Node = 'DOUT[2]~reg0'
Info: Total cell delay = 1.784 ns ( 26.29 % )
Info: Total interconnect delay = 5.003 ns ( 73.71 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "LOAD" to destination register is 2.781 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'LOAD'
Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X20_Y13_N2; Fanout = 1; REG Node = 'DOUT[2]~reg0'
Info: Total cell delay = 2.180 ns ( 78.39 % )
Info: Total interconnect delay = 0.601 ns ( 21.61 % )
Info: tco from clock "LOAD" to destination pin "DOUT[1]" through register "DOUT[1]~reg0" is 6.775 ns
Info: + Longest clock path from clock "LOAD" to source register is 2.781 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'LOAD'
Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y12_N2; Fanout = 1; REG Node = 'DOUT[1]~reg0'
Info: Total cell delay = 2.180 ns ( 78.39 % )
Info: Total interconnect delay = 0.601 ns ( 21.61 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 3.770 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y12_N2; Fanout = 1; REG Node = 'DOUT[1]~reg0'
Info: 2: + IC(1.662 ns) + CELL(2.108 ns) = 3.770 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'DOUT[1]'
Info: Total cell delay = 2.108 ns ( 55.92 % )
Info: Total interconnect delay = 1.662 ns ( 44.08 % )
Info: th for register "DOUT[1]~reg0" (data pin = "DIN[1]", clock pin = "LOAD") is -3.359 ns
Info: + Longest clock path from clock "LOAD" to destination register is 2.781 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'LOAD'
Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y12_N2; Fanout = 1; REG Node = 'DOUT[1]~reg0'
Info: Total cell delay = 2.180 ns ( 78.39 % )
Info: Total interconnect delay = 0.601 ns ( 21.61 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 6.155 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_106; Fanout = 1; PIN Node = 'DIN[1]'
Info: 2: + IC(4.571 ns) + CELL(0.115 ns) = 6.155 ns; Loc. = LC_X26_Y12_N2; Fanout = 1; REG Node = 'DOUT[1]~reg0'
Info: Total cell delay = 1.584 ns ( 25.74 % )
Info: Total interconnect delay = 4.571 ns ( 74.26 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Tue Jun 12 15:34:44 2007
Info: Elapsed time: 00:00:01
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