testfre.fit.eqn

用VHDL 语言描述频率计的设计

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--div2clk is div2clk at LC_X1_Y9_N2
--operation mode is normal

div2clk_lut_out = !div2clk;
div2clk = DFFEAS(div2clk_lut_out, CLKK, VCC, , , , , , );


--A1L5 is process1~0 at LC_X1_Y9_N5
--operation mode is normal

A1L5 = CLKK # div2clk;


--CLKK is CLKK at PIN_11
--operation mode is input

CLKK = INPUT();


--ENC is ENC at PIN_26
--operation mode is output

ENC = OUTPUT(div2clk);


--RSTC is RSTC at PIN_27
--operation mode is output

RSTC = OUTPUT(!A1L5);


--LOADC is LOADC at PIN_28
--operation mode is output

LOADC = OUTPUT(!div2clk);