sm.fit.eqn

用VHDL 语言描述频率计的设计

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--A1L6 is Mux~51 at LC_X1_Y10_N5
--operation mode is normal

A1L6 = I[1] & !I[3] & (!I[2] # !I[0]) # !I[1] & (I[3] $ (I[2]));


--A1L7 is Mux~52 at LC_X1_Y10_N2
--operation mode is normal

A1L7 = !I[3] & (I[1] & (I[0] # !I[2]) # !I[1] & I[0] & !I[2]);


--A1L8 is Mux~53 at LC_X1_Y10_N4
--operation mode is normal

A1L8 = I[1] & !I[3] & I[0] # !I[1] & (I[2] & !I[3] # !I[2] & (I[0]));


--A1L9 is Mux~54 at LC_X1_Y10_N9
--operation mode is normal

A1L9 = !I[3] & (I[1] & I[0] & I[2] # !I[1] & (I[0] $ I[2]));


--A1L10 is Mux~55 at LC_X1_Y10_N8
--operation mode is normal

A1L10 = !I[3] & I[1] & !I[0] & !I[2];


--A1L11 is Mux~56 at LC_X1_Y10_N7
--operation mode is normal

A1L11 = !I[3] & I[2] & (I[1] $ I[0]);


--A1L12 is Mux~57 at LC_X1_Y10_N6
--operation mode is normal

A1L12 = !I[3] & !I[1] & (I[0] $ I[2]);


--I[0] is I[0] at PIN_27
--operation mode is input

I[0] = INPUT();


--I[1] is I[1] at PIN_37
--operation mode is input

I[1] = INPUT();


--I[2] is I[2] at PIN_5
--operation mode is input

I[2] = INPUT();


--I[3] is I[3] at PIN_16
--operation mode is input

I[3] = INPUT();


--O[0] is O[0] at PIN_73
--operation mode is output

O[0] = OUTPUT(GND);


--O[1] is O[1] at PIN_10
--operation mode is output

O[1] = OUTPUT(A1L6);


--O[2] is O[2] at PIN_7
--operation mode is output

O[2] = OUTPUT(!A1L7);


--O[3] is O[3] at PIN_4
--operation mode is output

O[3] = OUTPUT(!A1L8);


--O[4] is O[4] at PIN_142
--operation mode is output

O[4] = OUTPUT(!A1L9);


--O[5] is O[5] at PIN_6
--operation mode is output

O[5] = OUTPUT(!A1L10);


--O[6] is O[6] at PIN_26
--operation mode is output

O[6] = OUTPUT(!A1L11);


--O[7] is O[7] at PIN_11
--operation mode is output

O[7] = OUTPUT(!A1L12);