📄 sm.tan.rpt
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Timing Analyzer report for SM
Sun Jun 17 22:28:42 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.746 ns ; I[1] ; O[6] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 11.746 ns ; I[1] ; O[6] ;
; N/A ; None ; 11.512 ns ; I[1] ; O[4] ;
; N/A ; None ; 11.352 ns ; I[1] ; O[3] ;
; N/A ; None ; 11.346 ns ; I[1] ; O[5] ;
; N/A ; None ; 11.232 ns ; I[1] ; O[7] ;
; N/A ; None ; 11.211 ns ; I[0] ; O[6] ;
; N/A ; None ; 10.986 ns ; I[0] ; O[4] ;
; N/A ; None ; 10.917 ns ; I[1] ; O[1] ;
; N/A ; None ; 10.910 ns ; I[1] ; O[2] ;
; N/A ; None ; 10.830 ns ; I[0] ; O[3] ;
; N/A ; None ; 10.816 ns ; I[0] ; O[5] ;
; N/A ; None ; 10.791 ns ; I[2] ; O[6] ;
; N/A ; None ; 10.694 ns ; I[0] ; O[7] ;
; N/A ; None ; 10.557 ns ; I[2] ; O[4] ;
; N/A ; None ; 10.401 ns ; I[2] ; O[3] ;
; N/A ; None ; 10.391 ns ; I[2] ; O[5] ;
; N/A ; None ; 10.388 ns ; I[0] ; O[2] ;
; N/A ; None ; 10.376 ns ; I[0] ; O[1] ;
; N/A ; None ; 10.277 ns ; I[2] ; O[7] ;
; N/A ; None ; 9.963 ns ; I[2] ; O[1] ;
; N/A ; None ; 9.959 ns ; I[2] ; O[2] ;
; N/A ; None ; 7.874 ns ; I[3] ; O[6] ;
; N/A ; None ; 7.640 ns ; I[3] ; O[4] ;
; N/A ; None ; 7.480 ns ; I[3] ; O[3] ;
; N/A ; None ; 7.474 ns ; I[3] ; O[5] ;
; N/A ; None ; 7.360 ns ; I[3] ; O[7] ;
; N/A ; None ; 7.045 ns ; I[3] ; O[1] ;
; N/A ; None ; 7.038 ns ; I[3] ; O[2] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sun Jun 17 22:28:42 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SM -c SM --timing_analysis_only
Info: Longest tpd from source pin "I[1]" to destination pin "O[6]" is 11.746 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_37; Fanout = 7; PIN Node = 'I[1]'
Info: 2: + IC(5.782 ns) + CELL(0.442 ns) = 7.699 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; COMB Node = 'Mux~56'
Info: 3: + IC(1.923 ns) + CELL(2.124 ns) = 11.746 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'O[6]'
Info: Total cell delay = 4.041 ns ( 34.40 % )
Info: Total interconnect delay = 7.705 ns ( 65.60 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Jun 17 22:28:42 2007
Info: Elapsed time: 00:00:01
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