cnt10.fit.eqn

用VHDL 语言描述频率计的设计

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--SS[0] is SS[0] at LC_X10_Y13_N0
--operation mode is normal

SS[0]_lut_out = !SS[0];
SS[0] = DFFEAS(SS[0]_lut_out, GLOBAL(CLK), !GLOBAL(RST), , EN, , , , );


--SS[1] is SS[1] at LC_X10_Y13_N6
--operation mode is normal

SS[1]_lut_out = SS[1] & (!SS[0]) # !SS[1] & SS[0] & (SS[2] # !SS[3]);
SS[1] = DFFEAS(SS[1]_lut_out, GLOBAL(CLK), !GLOBAL(RST), , EN, , , , );


--SS[2] is SS[2] at LC_X10_Y13_N5
--operation mode is normal

SS[2]_lut_out = SS[2] $ (SS[1] & EN & SS[0]);
SS[2] = DFFEAS(SS[2]_lut_out, GLOBAL(CLK), !GLOBAL(RST), , , , , , );


--SS[3] is SS[3] at LC_X10_Y13_N2
--operation mode is normal

SS[3]_lut_out = SS[1] & (SS[3] $ (SS[2] & SS[0])) # !SS[1] & SS[3] & (SS[2] # !SS[0]);
SS[3] = DFFEAS(SS[3]_lut_out, GLOBAL(CLK), !GLOBAL(RST), , EN, , , , );


--A1L9Q is OUTY~reg0 at LC_X10_Y13_N4
--operation mode is normal

A1L9Q_lut_out = !SS[1] & !SS[2] & SS[3] & SS[0];
A1L9Q = DFFEAS(A1L9Q_lut_out, GLOBAL(CLK), !GLOBAL(RST), , EN, , , , );


--CLK is CLK at PIN_17
--operation mode is input

CLK = INPUT();


--RST is RST at PIN_16
--operation mode is input

RST = INPUT();


--EN is EN at PIN_131
--operation mode is input

EN = INPUT();


--OUTX[0] is OUTX[0] at PIN_132
--operation mode is output

OUTX[0] = OUTPUT(SS[0]);


--OUTX[1] is OUTX[1] at PIN_130
--operation mode is output

OUTX[1] = OUTPUT(SS[1]);


--OUTX[2] is OUTX[2] at PIN_2
--operation mode is output

OUTX[2] = OUTPUT(SS[2]);


--OUTX[3] is OUTX[3] at PIN_127
--operation mode is output

OUTX[3] = OUTPUT(SS[3]);


--OUTY is OUTY at PIN_128
--operation mode is output

OUTY = OUTPUT(A1L9Q);