cnt10.tan.rpt

用VHDL 语言描述频率计的设计

; tsu                                                             ;
+-------+--------------+------------+------+-----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To        ; To Clock ;
+-------+--------------+------------+------+-----------+----------+
; N/A   ; None         ; 4.684 ns   ; EN   ; SS[0]     ; CLK      ;
; N/A   ; None         ; 4.684 ns   ; EN   ; SS[1]     ; CLK      ;
; N/A   ; None         ; 4.684 ns   ; EN   ; SS[3]     ; CLK      ;
; N/A   ; None         ; 4.684 ns   ; EN   ; OUTY~reg0 ; CLK      ;
; N/A   ; None         ; 4.266 ns   ; EN   ; SS[2]     ; CLK      ;
+-------+--------------+------------+------+-----------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+-----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To      ; From Clock ;
+-------+--------------+------------+-----------+---------+------------+
; N/A   ; None         ; 7.193 ns   ; SS[2]     ; OUTX[2] ; CLK        ;
; N/A   ; None         ; 6.796 ns   ; SS[3]     ; OUTX[3] ; CLK        ;
; N/A   ; None         ; 6.709 ns   ; SS[0]     ; OUTX[0] ; CLK        ;
; N/A   ; None         ; 6.398 ns   ; SS[1]     ; OUTX[1] ; CLK        ;
; N/A   ; None         ; 6.393 ns   ; OUTY~reg0 ; OUTY    ; CLK        ;
+-------+--------------+------------+-----------+---------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -4.214 ns ; EN   ; SS[2]     ; CLK      ;
; N/A           ; None        ; -4.632 ns ; EN   ; SS[0]     ; CLK      ;
; N/A           ; None        ; -4.632 ns ; EN   ; SS[1]     ; CLK      ;
; N/A           ; None        ; -4.632 ns ; EN   ; SS[3]     ; CLK      ;
; N/A           ; None        ; -4.632 ns ; EN   ; OUTY~reg0 ; CLK      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Jun 12 15:27:03 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CNT10 -c CNT10 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "SS[1]" and destination register "SS[3]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.303 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y13_N6; Fanout = 5; REG Node = 'SS[1]'
            Info: 2: + IC(0.565 ns) + CELL(0.738 ns) = 1.303 ns; Loc. = LC_X10_Y13_N2; Fanout = 4; REG Node = 'SS[3]'
            Info: Total cell delay = 0.738 ns ( 56.64 % )
            Info: Total interconnect delay = 0.565 ns ( 43.36 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.767 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N2; Fanout = 4; REG Node = 'SS[3]'
                Info: Total cell delay = 2.180 ns ( 78.79 % )
                Info: Total interconnect delay = 0.587 ns ( 21.21 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.767 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N6; Fanout = 5; REG Node = 'SS[1]'
                Info: Total cell delay = 2.180 ns ( 78.79 % )
                Info: Total interconnect delay = 0.587 ns ( 21.21 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "SS[0]" (data pin = "EN", clock pin = "CLK") is 4.684 ns
    Info: + Longest pin to register delay is 7.414 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_131; Fanout = 5; PIN Node = 'EN'
        Info: 2: + IC(5.072 ns) + CELL(0.867 ns) = 7.414 ns; Loc. = LC_X10_Y13_N0; Fanout = 6; REG Node = 'SS[0]'
        Info: Total cell delay = 2.342 ns ( 31.59 % )
        Info: Total interconnect delay = 5.072 ns ( 68.41 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.767 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N0; Fanout = 6; REG Node = 'SS[0]'
        Info: Total cell delay = 2.180 ns ( 78.79 % )
        Info: Total interconnect delay = 0.587 ns ( 21.21 % )
Info: tco from clock "CLK" to destination pin "OUTX[2]" through register "SS[2]" is 7.193 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.767 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N5; Fanout = 5; REG Node = 'SS[2]'
        Info: Total cell delay = 2.180 ns ( 78.79 % )
        Info: Total interconnect delay = 0.587 ns ( 21.21 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.202 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y13_N5; Fanout = 5; REG Node = 'SS[2]'
        Info: 2: + IC(2.078 ns) + CELL(2.124 ns) = 4.202 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'OUTX[2]'
        Info: Total cell delay = 2.124 ns ( 50.55 % )
        Info: Total interconnect delay = 2.078 ns ( 49.45 % )
Info: th for register "SS[2]" (data pin = "EN", clock pin = "CLK") is -4.214 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.767 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X10_Y13_N5; Fanout = 5; REG Node = 'SS[2]'
        Info: Total cell delay = 2.180 ns ( 78.79 % )
        Info: Total interconnect delay = 0.587 ns ( 21.21 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.996 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_131; Fanout = 5; PIN Node = 'EN'
        Info: 2: + IC(5.043 ns) + CELL(0.478 ns) = 6.996 ns; Loc. = LC_X10_Y13_N5; Fanout = 5; REG Node = 'SS[2]'
        Info: Total cell delay = 1.953 ns ( 27.92 % )
        Info: Total interconnect delay = 5.043 ns ( 72.08 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jun 12 15:27:03 2007
    Info: Elapsed time: 00:00:01