hh.tan.rpt

用VHDL 语言描述频率计的设计

; N/A   ; None         ; 17.438 ns  ; REG4:R2|DOUT[0] ; LED1[1] ; CLK1       ;
; N/A   ; None         ; 17.427 ns  ; REG4:R1|DOUT[2] ; LED0[5] ; CLK1       ;
; N/A   ; None         ; 17.411 ns  ; REG4:R3|DOUT[1] ; LED2[7] ; CLK1       ;
; N/A   ; None         ; 17.382 ns  ; REG4:R3|DOUT[3] ; LED2[5] ; CLK1       ;
; N/A   ; None         ; 17.354 ns  ; REG4:R1|DOUT[0] ; LED0[1] ; CLK1       ;
; N/A   ; None         ; 17.348 ns  ; REG4:R1|DOUT[3] ; LED0[4] ; CLK1       ;
; N/A   ; None         ; 17.321 ns  ; REG4:R2|DOUT[2] ; LED1[7] ; CLK1       ;
; N/A   ; None         ; 17.315 ns  ; REG4:R1|DOUT[0] ; LED0[3] ; CLK1       ;
; N/A   ; None         ; 17.305 ns  ; REG4:R2|DOUT[3] ; LED1[3] ; CLK1       ;
; N/A   ; None         ; 17.302 ns  ; REG4:R2|DOUT[1] ; LED1[6] ; CLK1       ;
; N/A   ; None         ; 17.282 ns  ; REG4:R4|DOUT[1] ; LED3[4] ; CLK1       ;
; N/A   ; None         ; 17.271 ns  ; REG4:R4|DOUT[1] ; LED3[1] ; CLK1       ;
; N/A   ; None         ; 17.266 ns  ; REG4:R4|DOUT[1] ; LED3[3] ; CLK1       ;
; N/A   ; None         ; 17.258 ns  ; REG4:R1|DOUT[0] ; LED0[5] ; CLK1       ;
; N/A   ; None         ; 17.203 ns  ; REG4:R3|DOUT[0] ; LED2[6] ; CLK1       ;
; N/A   ; None         ; 17.203 ns  ; REG4:R3|DOUT[0] ; LED2[4] ; CLK1       ;
; N/A   ; None         ; 17.185 ns  ; REG4:R2|DOUT[3] ; LED1[7] ; CLK1       ;
; N/A   ; None         ; 17.179 ns  ; REG4:R3|DOUT[1] ; LED2[3] ; CLK1       ;
; N/A   ; None         ; 17.178 ns  ; REG4:R3|DOUT[1] ; LED2[5] ; CLK1       ;
; N/A   ; None         ; 17.109 ns  ; REG4:R2|DOUT[3] ; LED1[4] ; CLK1       ;
; N/A   ; None         ; 17.041 ns  ; REG4:R3|DOUT[2] ; LED2[4] ; CLK1       ;
; N/A   ; None         ; 17.040 ns  ; REG4:R3|DOUT[2] ; LED2[6] ; CLK1       ;
; N/A   ; None         ; 17.001 ns  ; REG4:R2|DOUT[1] ; LED1[3] ; CLK1       ;
; N/A   ; None         ; 16.994 ns  ; REG4:R2|DOUT[1] ; LED1[7] ; CLK1       ;
; N/A   ; None         ; 16.974 ns  ; REG4:R1|DOUT[2] ; LED0[3] ; CLK1       ;
; N/A   ; None         ; 16.966 ns  ; REG4:R2|DOUT[1] ; LED1[2] ; CLK1       ;
; N/A   ; None         ; 16.936 ns  ; REG4:R4|DOUT[3] ; LED3[4] ; CLK1       ;
; N/A   ; None         ; 16.936 ns  ; REG4:R3|DOUT[3] ; LED2[6] ; CLK1       ;
; N/A   ; None         ; 16.928 ns  ; REG4:R4|DOUT[0] ; LED3[1] ; CLK1       ;
; N/A   ; None         ; 16.921 ns  ; REG4:R4|DOUT[2] ; LED3[3] ; CLK1       ;
; N/A   ; None         ; 16.850 ns  ; REG4:R3|DOUT[1] ; LED2[2] ; CLK1       ;
; N/A   ; None         ; 16.848 ns  ; REG4:R3|DOUT[0] ; LED2[1] ; CLK1       ;
; N/A   ; None         ; 16.837 ns  ; REG4:R3|DOUT[2] ; LED2[3] ; CLK1       ;
; N/A   ; None         ; 16.741 ns  ; REG4:R3|DOUT[1] ; LED2[6] ; CLK1       ;
; N/A   ; None         ; 16.740 ns  ; REG4:R3|DOUT[1] ; LED2[4] ; CLK1       ;
; N/A   ; None         ; 16.659 ns  ; REG4:R2|DOUT[2] ; LED1[3] ; CLK1       ;
; N/A   ; None         ; 16.402 ns  ; REG4:R3|DOUT[3] ; LED2[4] ; CLK1       ;
+-------+--------------+------------+-----------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Jun 21 16:05:56 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off hh -c hh --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK1" is an undefined clock
    Info: Assuming node "UCLK" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CNT10:C2|OUTY" as buffer
    Info: Detected ripple clock "CNT10:C1|OUTY" as buffer
    Info: Detected ripple clock "CNT10:C0|OUTY" as buffer
    Info: Detected ripple clock "TESTFRE:T|div2clk" as buffer
Info: Clock "CLK1" Internal fmax is restricted to 275.03 MHz between source register "TESTFRE:T|div2clk" and destination register "TESTFRE:T|div2clk"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.027 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T|div2clk'
            Info: 2: + IC(0.549 ns) + CELL(0.478 ns) = 1.027 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T|div2clk'
            Info: Total cell delay = 0.478 ns ( 46.54 % )
            Info: Total interconnect delay = 0.549 ns ( 53.46 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK1" to destination register is 7.750 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_130; Fanout = 2; CLK Node = 'CLK1'
                Info: 2: + IC(5.564 ns) + CELL(0.711 ns) = 7.750 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T|div2clk'
                Info: Total cell delay = 2.186 ns ( 28.21 % )
                Info: Total interconnect delay = 5.564 ns ( 71.79 % )
            Info: - Longest clock path from clock "CLK1" to source register is 7.750 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_130; Fanout = 2; CLK Node = 'CLK1'
                Info: 2: + IC(5.564 ns) + CELL(0.711 ns) = 7.750 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T|div2clk'
                Info: Total cell delay = 2.186 ns ( 28.21 % )
                Info: Total interconnect delay = 5.564 ns ( 71.79 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "UCLK" Internal fmax is restricted to 275.03 MHz between source register "CNT10:C2|SS[0]" and destination register "CNT10:C2|SS[1]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.319 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y6_N2; Fanout = 6; REG Node = 'CNT10:C2|SS[0]'
            Info: 2: + IC(0.581 ns) + CELL(0.738 ns) = 1.319 ns; Loc. = LC_X26_Y6_N5; Fanout = 5; REG Node = 'CNT10:C2|SS[1]'
            Info: Total cell delay = 0.738 ns ( 55.95 % )
            Info: Total interconnect delay = 0.581 ns ( 44.05 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "UCLK" to destination register is 12.081 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'UCLK'
                Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N5; Fanout = 5; REG Node = 'CNT10:C0|OUTY'
                Info: 3: + IC(3.502 ns) + CELL(0.935 ns) = 7.399 ns; Loc. = LC_X25_Y6_N4; Fanout = 5; REG Node = 'CNT10:C1|OUTY'
                Info: 4: + IC(3.971 ns) + CELL(0.711 ns) = 12.081 ns; Loc. = LC_X26_Y6_N5; Fanout = 5; REG Node = 'CNT10:C2|SS[1]'
                Info: Total cell delay = 4.050 ns ( 33.52 % )
                Info: Total interconnect delay = 8.031 ns ( 66.48 % )
            Info: - Longest clock path from clock "UCLK" to source register is 12.081 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'UCLK'
                Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N5; Fanout = 5; REG Node = 'CNT10:C0|OUTY'
                Info: 3: + IC(3.502 ns) + CELL(0.935 ns) = 7.399 ns; Loc. = LC_X25_Y6_N4; Fanout = 5; REG Node = 'CNT10:C1|OUTY'
                Info: 4: + IC(3.971 ns) + CELL(0.711 ns) = 12.081 ns; Loc. = LC_X26_Y6_N2; Fanout = 6; REG Node = 'CNT10:C2|SS[0]'
                Info: Total cell delay = 4.050 ns ( 33.52 % )
                Info: Total interconnect delay = 8.031 ns ( 66.48 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLK1" to destination pin "LED0[2]" through register "REG4:R1|DOUT[3]" is 18.829 ns
    Info: + Longest clock path from clock "CLK1" to source register is 12.531 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_130; Fanout = 2; CLK Node = 'CLK1'
        Info: 2: + IC(5.564 ns) + CELL(0.935 ns) = 7.974 ns; Loc. = LC_X10_Y6_N2; Fanout = 37; REG Node = 'TESTFRE:T|div2clk'
        Info: 3: + IC(3.846 ns) + CELL(0.711 ns) = 12.531 ns; Loc. = LC_X8_Y5_N5; Fanout = 7; REG Node = 'REG4:R1|DOUT[3]'
        Info: Total cell delay = 3.121 ns ( 24.91 % )
        Info: Total interconnect delay = 9.410 ns ( 75.09 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.074 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y5_N5; Fanout = 7; REG Node = 'REG4:R1|DOUT[3]'
        Info: 2: + IC(0.760 ns) + CELL(0.590 ns) = 1.350 ns; Loc. = LC_X8_Y5_N9; Fanout = 1; COMB Node = 'SM:SM1|O[2]~213'
        Info: 3: + IC(2.616 ns) + CELL(2.108 ns) = 6.074 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'LED0[2]'
        Info: Total cell delay = 2.698 ns ( 44.42 % )
        Info: Total interconnect delay = 3.376 ns ( 55.58 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Jun 21 16:05:57 2007
    Info: Elapsed time: 00:00:01