time_going.syr

用VHDL写的运动计时表程序

=========================================================================
Final Results
RTL Top Level Output File Name     : time_going.ngr
Top Level Output File Name         : time_going
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 51

Cell Usage :
# BELS                             : 130
#      LUT1                        : 3
#      LUT2                        : 26
#      LUT2_L                      : 4
#      LUT3                        : 36
#      LUT3_D                      : 1
#      LUT3_L                      : 9
#      LUT4                        : 8
#      LUT4_D                      : 3
#      LUT4_L                      : 36
#      MUXF5                       : 4
# FlipFlops/Latches                : 26
#      FDC                         : 2
#      FDCP                        : 24
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 50
#      IBUF                        : 26
#      OBUF                        : 24
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40cs144-6 

 Number of Slices:                      68  out of    256    26%  
 Number of Slice Flip Flops:            26  out of    512     5%  
 Number of 4 input LUTs:               126  out of    512    24%  
 Number of bonded IOBs:                 51  out of     88    57%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk<0>                             | BUFGP                  | 9     |
second_60/cin_min                  | NONE                   | 9     |
minute_60/cin_0                    | NONE                   | 8     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.639ns (Maximum Frequency: 274.763MHz)
   Minimum input arrival time before clock: 3.804ns
   Maximum output required time after clock: 4.864ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk<0>'
  Clock period: 3.323ns (frequency: 300.933MHz)
  Total number of paths / destination ports: 69 / 9
-------------------------------------------------------------------------
Delay:               3.323ns (Levels of Logic = 3)
  Source:            second_60/out_sec_3 (FF)
  Destination:       second_60/out_sec_5 (FF)
  Source Clock:      clk<0> rising
  Destination Clock: clk<0> rising

  Data Path: second_60/out_sec_3 to second_60/out_sec_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCP:C->Q             6   0.449   0.812  second_60/out_sec_3 (second_60/out_sec_3)
     LUT4_D:I0->O          5   0.347   0.597  second_60/Ker11 (second_60/N1)
     LUT4_L:I2->LO         1   0.347   0.132  second_60/_n000519 (second_60/_n0005_map489)
     LUT4_L:I3->LO         1   0.347   0.000  second_60/_n000547 (second_60/_n0005)
     FDCP:D                    0.293          second_60/out_sec_6
    ----------------------------------------
    Total                      3.323ns (1.783ns logic, 1.540ns route)
                                       (53.7% logic, 46.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'second_60/cin_min'
  Clock period: 3.639ns (frequency: 274.763MHz)
  Total number of paths / destination ports: 80 / 9
-------------------------------------------------------------------------
Delay:               3.639ns (Levels of Logic = 3)
  Source:            minute_60/out_min_0 (FF)
  Destination:       minute_60/out_min_6 (FF)
  Source Clock:      second_60/cin_min rising
  Destination Clock: second_60/cin_min rising

  Data Path: minute_60/out_min_0 to minute_60/out_min_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCP:C->Q             8   0.449   0.845  minute_60/out_min_0 (minute_60/out_min_0)
     LUT4_D:I0->O          5   0.347   0.597  minute_60/_n00131 (minute_60/_n0013)
     LUT4:I2->O            1   0.347   0.414  minute_60/_n000623 (minute_60/_n0006_map607)
     LUT4_L:I3->LO         1   0.347   0.000  minute_60/_n000664 (minute_60/_n0006)
     FDCP:D                    0.293          minute_60/out_min_6
    ----------------------------------------
    Total                      3.639ns (1.783ns logic, 1.857ns route)
                                       (49.0% logic, 51.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'minute_60/cin_0'
  Clock period: 3.352ns (frequency: 298.329MHz)
  Total number of paths / destination ports: 82 / 8
-------------------------------------------------------------------------
Delay:               3.352ns (Levels of Logic = 3)
  Source:            hour_24/out_0 (FF)
  Destination:       hour_24/out_0 (FF)
  Source Clock:      minute_60/cin_0 rising
  Destination Clock: minute_60/cin_0 rising

  Data Path: hour_24/out_0 to hour_24/out_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCP:C->Q             9   0.449   0.863  hour_24/out_0 (hour_24/out_0)
     LUT3:I0->O            4   0.347   0.580  hour_24/Ker01 (hour_24/N01)
     LUT4_L:I2->LO         1   0.347   0.127  hour_24/_n000627 (hour_24/_n0006_map573)
     LUT3_L:I2->LO         1   0.347   0.000  hour_24/_n000641 (hour_24/_n0006)
     FDCP:D                    0.293          hour_24/out_4
    ----------------------------------------
    Total                      3.352ns (1.783ns logic, 1.569ns route)
                                       (53.2% logic, 46.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk<0>'
  Total number of paths / destination ports: 22 / 8
-------------------------------------------------------------------------
Offset:              3.446ns (Levels of Logic = 3)
  Source:            load<0> (PAD)
  Destination:       second_60/out_sec_5 (FF)
  Destination Clock: clk<0> rising

  Data Path: load<0> to second_60/out_sec_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            81   0.653   1.063  load_0_IBUF (load)
     LUT2:I1->O            2   0.347   0.744  second_60/out_sec_6__n00011 (second_60/_n0005_map480)
     LUT4_L:I0->LO         1   0.347   0.000  second_60/_n000547 (second_60/_n0005)
     FDCP:D                    0.293          second_60/out_sec_6
    ----------------------------------------
    Total                      3.446ns (1.640ns logic, 1.806ns route)
                                       (47.6% logic, 52.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'second_60/cin_min'
  Total number of paths / destination ports: 22 / 8
-------------------------------------------------------------------------
Offset:              3.651ns (Levels of Logic = 4)
  Source:            load<0> (PAD)
  Destination:       minute_60/out_min_5 (FF)
  Destination Clock: second_60/cin_min rising

  Data Path: load<0> to minute_60/out_min_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            81   0.653   1.123  load_0_IBUF (load)
     LUT3_L:I0->LO         1   0.347   0.127  minute_60/_n000717_SW0 (N502)
     LUT3:I2->O            1   0.347   0.414  minute_60/_n000762_SW1 (N511)
     LUT4_L:I3->LO         1   0.347   0.000  minute_60/_n000762 (minute_60/_n0007)
     FDCP:D                    0.293          minute_60/out_min_5
    ----------------------------------------
    Total                      3.651ns (1.987ns logic, 1.664ns route)
                                       (54.4% logic, 45.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'minute_60/cin_0'
  Total number of paths / destination ports: 26 / 8
-------------------------------------------------------------------------
Offset:              3.804ns (Levels of Logic = 4)
  Source:            load<0> (PAD)
  Destination:       hour_24/out_6 (FF)
  Destination Clock: minute_60/cin_0 rising

  Data Path: load<0> to hour_24/out_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            81   0.653   1.123  load_0_IBUF (load)
     LUT2_L:I0->LO         1   0.347   0.127  hour_24/Ker7_SW0 (N308)
     LUT4:I2->O            3   0.347   0.567  hour_24/Ker7 (hour_24/N7)
     LUT4_L:I3->LO         1   0.347   0.000  hour_24/_n000453 (hour_24/_n0004)
     FDCP:D                    0.293          hour_24/out_6
    ----------------------------------------
    Total                      3.804ns (1.987ns logic, 1.817ns route)
                                       (52.2% logic, 47.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk<0>'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.813ns (Levels of Logic = 1)
  Source:            second_60/out_sec_4 (FF)
  Destination:       out_sec<4> (PAD)
  Source Clock:      clk<0> rising

  Data Path: second_60/out_sec_4 to out_sec<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCP:C->Q             8   0.449   0.621  second_60/out_sec_4 (second_60/out_sec_4)
     OBUF:I->O                 3.743          out_sec_4_OBUF (out_sec<4>)
    ----------------------------------------
    Total                      4.813ns (4.192ns logic, 0.621ns route)
                                       (87.1% logic, 12.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'second_60/cin_min'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.846ns (Levels of Logic = 1)
  Source:            minute_60/out_min_4 (FF)
  Destination:       out_min<4> (PAD)
  Source Clock:      second_60/cin_min rising

  Data Path: minute_60/out_min_4 to out_min<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCP:C->Q            10   0.449   0.655  minute_60/out_min_4 (minute_60/out_min_4)
     OBUF:I->O                 3.743          out_min_4_OBUF (out_min<4>)
    ----------------------------------------
    Total                      4.846ns (4.192ns logic, 0.655ns route)
                                       (86.5% logic, 13.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'minute_60/cin_0'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.864ns (Levels of Logic = 1)
  Source:            hour_24/out_3 (FF)
  Destination:       out<3> (PAD)
  Source Clock:      minute_60/cin_0 rising

  Data Path: hour_24/out_3 to out<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCP:C->Q            11   0.449   0.672  hour_24/out_3 (hour_24/out_3)
     OBUF:I->O                 3.743          out_3_OBUF (out<3>)
    ----------------------------------------
    Total                      4.864ns (4.192ns logic, 0.672ns route)
                                       (86.2% logic, 13.8% route)

=========================================================================
CPU : 30.06 / 33.20 s | Elapsed : 30.00 / 34.00 s
 
--> 

Total memory usage is 106928 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   24 (   0 filtered)
Number of infos    :    9 (   0 filtered)