time_going.syr

用VHDL写的运动计时表程序

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 2.90 s | Elapsed : 0.00 / 3.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 2.91 s | Elapsed : 0.00 / 3.00 s
 
--> Reading design: time_going.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "time_going.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "time_going"
Output Format                      : NGC
Target Device                      : xc2v40-6-cs144

---- Source Options
Top Module Name                    : time_going
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : time_going.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "time60.v" in library work
Compiling verilog file "time24.v" in library work
Module <time60> compiled
Compiling verilog file "sec60.v" in library work
Module <time24> compiled
Compiling verilog file "time_go.v" in library work
Module <sec60> compiled
Module <time_going> compiled
No errors in compilation
Analysis of file <"time_going.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <time_going>.
Module <time_going> is correct for synthesis.
 
Analyzing module <time24>.
WARNING:Xst:1467 - "time24.v" line 0: Reset or set value is not constant in <out[7]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time24.v" line 0: Reset or set value is not constant in <out[6]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time24.v" line 0: Reset or set value is not constant in <out[5]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time24.v" line 0: Reset or set value is not constant in <out[4]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time24.v" line 0: Reset or set value is not constant in <out[3]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time24.v" line 0: Reset or set value is not constant in <out[2]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time24.v" line 0: Reset or set value is not constant in <out[1]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time24.v" line 0: Reset or set value is not constant in <out[0]>. It could involve simulation mismatches
Module <time24> is correct for synthesis.
 
Analyzing module <time60>.
WARNING:Xst:1467 - "time60.v" line 35: Reset or set value is not constant in <out_min[7]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time60.v" line 35: Reset or set value is not constant in <out_min[6]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time60.v" line 35: Reset or set value is not constant in <out_min[5]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time60.v" line 35: Reset or set value is not constant in <out_min[4]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time60.v" line 35: Reset or set value is not constant in <out_min[3]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time60.v" line 35: Reset or set value is not constant in <out_min[2]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time60.v" line 35: Reset or set value is not constant in <out_min[1]>. It could involve simulation mismatches
WARNING:Xst:1467 - "time60.v" line 35: Reset or set value is not constant in <out_min[0]>. It could involve simulation mismatches
Module <time60> is correct for synthesis.
 
Analyzing module <sec60>.
WARNING:Xst:1467 - "sec60.v" line 34: Reset or set value is not constant in <out_sec[7]>. It could involve simulation mismatches
WARNING:Xst:1467 - "sec60.v" line 34: Reset or set value is not constant in <out_sec[6]>. It could involve simulation mismatches
WARNING:Xst:1467 - "sec60.v" line 34: Reset or set value is not constant in <out_sec[5]>. It could involve simulation mismatches
WARNING:Xst:1467 - "sec60.v" line 34: Reset or set value is not constant in <out_sec[4]>. It could involve simulation mismatches
WARNING:Xst:1467 - "sec60.v" line 34: Reset or set value is not constant in <out_sec[3]>. It could involve simulation mismatches
WARNING:Xst:1467 - "sec60.v" line 34: Reset or set value is not constant in <out_sec[2]>. It could involve simulation mismatches
WARNING:Xst:1467 - "sec60.v" line 34: Reset or set value is not constant in <out_sec[1]>. It could involve simulation mismatches
WARNING:Xst:1467 - "sec60.v" line 34: Reset or set value is not constant in <out_sec[0]>. It could involve simulation mismatches
Module <sec60> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sec60>.
    Related source file is "sec60.v".
    Found 4x1-bit ROM for signal <$n0003>.
    Found 8-bit register for signal <out_sec>.
    Found 1-bit register for signal <cin_min>.
    Found 4-bit adder for signal <$n0000> created at line 49.
    Found 8-bit adder for signal <$n0001> created at line 53.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0010>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0011>.
    Found 4-bit comparator greatequal for signal <$n0012> created at line 39.
    Found 4-bit comparator greatequal for signal <$n0013> created at line 41.
    Summary:
	inferred   1 ROM(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <sec60> synthesized.


Synthesizing Unit <time60>.
    Related source file is "time60.v".
    Found 4x1-bit ROM for signal <$n0003>.
    Found 8-bit register for signal <out_min>.
    Found 1-bit register for signal <cin<0>>.
    Found 4-bit adder for signal <$n0000> created at line 49.
    Found 8-bit adder for signal <$n0001> created at line 54.
    Found 1-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0010>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0011>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0012>.
    Found 4-bit comparator greatequal for signal <$n0014> created at line 42.
    Summary:
	inferred   1 ROM(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <time60> synthesized.


Synthesizing Unit <time24>.
    Related source file is "time24.v".
INFO:Xst:1608 - Relative priorities of control signals on register <out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
INFO:Xst:1608 - Relative priorities of control signals on register <out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
INFO:Xst:1608 - Relative priorities of control signals on register <out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
INFO:Xst:1608 - Relative priorities of control signals on register <out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
INFO:Xst:1608 - Relative priorities of control signals on register <out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
INFO:Xst:1608 - Relative priorities of control signals on register <out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
INFO:Xst:1608 - Relative priorities of control signals on register <out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
INFO:Xst:1608 - Relative priorities of control signals on register <out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
    Found 8-bit register for signal <out>.
    Found 4-bit adder for signal <$n0000> created at line 45.
    Found 8-bit adder for signal <$n0001> created at line 50.
    Found 4-bit comparator greatequal for signal <$n0011> created at line 42.
    Found 4-bit comparator greatequal for signal <$n0012> created at line 47.
    Found 4-bit comparator greatequal for signal <$n0013> created at line 47.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <time24> synthesized.


Synthesizing Unit <time_going>.
    Related source file is "time_go.v".
Unit <time_going> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 2
 4x1-bit ROM                                           : 2
# Adders/Subtractors                                   : 6
 4-bit adder                                           : 3
 8-bit adder                                           : 3
# Registers                                            : 26
 1-bit register                                        : 26
# Comparators                                          : 6
 4-bit comparator greatequal                           : 6
# Multiplexers                                         : 8
 1-bit 4-to-1 multiplexer                              : 8

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 2
 4x1-bit ROM                                           : 2
# Adders/Subtractors                                   : 6
 4-bit adder                                           : 3
 8-bit adder                                           : 3
# Registers                                            : 3
 Flip-Flops                                            : 3
# Comparators                                          : 6
 4-bit comparator greatequal                           : 6
# Multiplexers                                         : 8
 1-bit 4-to-1 multiplexer                              : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '2v40.nph' in environment D:\Xilinx ISE 8.1.

Optimizing unit <time_going> ...

Optimizing unit <sec60> ...

Optimizing unit <time60> ...

Optimizing unit <time24> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block time_going, actual ratio is 28.

=========================================================================
*                            Final Report                               *