washer.vhd

用VHDL编的洗衣机程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity washer is
	port(
		 clk,model,s_and_p,power: in std_logic;
		 clk50out,clk1000out: out std_logic;
		 ctrlout: out std_logic_vector(2 downto 0);
		 nextstaout: out std_logic;
		 show_count: out std_logic_vector(5 downto 0);
		 number:out std_logic_vector(6 downto 0);
		 seg:out std_logic_vector(5 downto 0)
		);
end washer;

architecture washer_1 of washer is
component modelctrl
	port(
		 model: in std_logic;
		 stanum: out std_logic_vector(6 downto 0);
		 ctrl: out std_logic_vector(2 downto 0)
		);
end component; 

component div
	port(
		 clk: in std_logic;
		 clk1000,clk50: out std_logic
		);
end component;

component counter
	port(
		 clk50,pause_c,read: in std_logic;
		 count_c: in std_logic_vector(5 downto 0);
		 set0,nextsta_c:out std_logic;
		 counter_out: out std_logic_vector(5 downto 0)
		 );
end component;
	
component washer_statement
	port(
		 s_and_p,clk50,nextsta_w,power_w: in std_logic;
		 pause_w: out std_logic;
		 statectrl: in std_logic_vector(2 downto 0);
		 count_w: out std_logic_vector(5 downto 0)
		);
end component;

component seg7
	port(
     	 clk1000,power_s:in std_logic;
	 	 num3: in std_logic_vector(6 downto 0);
     	 counter_in:in std_logic_vector(5 downto 0);
     	 num:out std_logic_vector(6 downto 0);
     	 seg:out std_logic_vector(5 downto 0)
    	);
end component;

signal ctrl: std_logic_vector(2 downto 0);
signal clk50,clk1000,read_set0,nextsta,pause: std_logic;
signal counter_in_out: std_logic_vector(5 downto 0);
signal count: std_logic_vector(5 downto 0);
signal numconnect: std_logic_vector(6 downto 0);

begin
ia: modelctrl port map(model=>model,ctrl=>ctrl,stanum=>numconnect);
ib: washer_statement port map(s_and_p=>s_and_p,clk50=>clk50,nextsta_w=>nextsta,statectrl=>ctrl,count_w=>count,pause_w=>pause,power_w=>power);
ic: div port map(clk=>clk,clk50=>clk50,clk1000=>clk1000);
id: counter port map(clk50=>clk50,pause_c=>pause,read=>read_set0,count_c=>count,set0=>read_set0,nextsta_c=>nextsta,counter_out=>counter_in_out);
ie: seg7 port map(clk1000=>clk1000,counter_in=>counter_in_out,num=>number,seg=>seg,num3=>numconnect,power_s=>power);
show_count<=counter_in_out;
clk50out<=clk50;
clk1000out<=clk1000;
ctrlout<=ctrl;
nextstaout<=nextsta;
end washer_1;