counter.vhd

来自「用VHDL编的洗衣机程序」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is 
	port(
		 clk50,pause_c,read: in std_logic;
		 count_c: in std_logic_vector(5 downto 0);
		 set0,nextsta_c:out std_logic;
		 counter_out: out std_logic_vector(5 downto 0)
		 );
end counter;

architecture counter_1 of counter is
signal count_1: std_logic_vector(5 downto 0);
begin
  process(clk50,pause_c)
   begin
	if pause_c='1' then
		count_1<=count_1;
	else 
		if clk50'event and clk50='1' then	
			if (read='1') then
				count_1<=count_c;
				set0<='0';
				nextsta_c<='0';
			else  
               	  if count_1="000000" then
				  	nextsta_c<='1';
					set0<='1';
				  else
					count_1<=count_1-1;
			      end if;
		     end if;
	    end if;
	end if;
	counter_out<=count_1;
  end process;
end counter_1;