washer.map.qmsg

用VHDL编的洗衣机程序

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num1 seg7.vhd(42) " "Warning: VHDL Process Statement warning at seg7.vhd(42): signal num1 is in statement, but is not in sensitivity list" {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num2 seg7.vhd(45) " "Warning: VHDL Process Statement warning at seg7.vhd(45): signal num2 is in statement, but is not in sensitivity list" {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num3 seg7.vhd(48) " "Warning: VHDL Process Statement warning at seg7.vhd(48): signal num3 is in statement, but is not in sensitivity list" {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "seg seg7.vhd(36) " "Warning: VHDL Process Statement warning at seg7.vhd(36): signal or variable seg may not be assigned a new value in every possible path through the Process Statement. Signal or variable seg holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "num seg7.vhd(36) " "Warning: VHDL Process Statement warning at seg7.vhd(36): signal or variable num may not be assigned a new value in every possible path through the Process Statement. Signal or variable num holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 36 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg7:ie\|seg\[3\] " "Warning: LATCH primitive seg7:ie\|seg\[3\] is permanently enabled" {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg7:ie\|seg\[2\] " "Warning: LATCH primitive seg7:ie\|seg\[2\] is permanently enabled" {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg7:ie\|seg\[1\] " "Warning: LATCH primitive seg7:ie\|seg\[1\] is permanently enabled" {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg7:ie\|seg\[0\] " "Warning: LATCH primitive seg7:ie\|seg\[0\] is permanently enabled" {  } { { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 12 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "c:/altera/quartus41/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "c:/altera/quartus41/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "c:/altera/quartus41/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "c:/altera/quartus41/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_PREPROCESS_STAT" "\|washer\|washer_statement:ib\|present_state 5 0 " "Info: State machine \|washer\|washer_statement:ib\|present_state contains 5 states and 0 state bits" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|washer\|washer_statement:ib\|present_state " "Info: Selected Auto state machine encoding method for state machine \|washer\|washer_statement:ib\|present_state" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|washer\|washer_statement:ib\|present_state " "Info: Encoding result for state machine \|washer\|washer_statement:ib\|present_state" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "washer_statement:ib\|present_state~9 " "Info: Encoded state bit washer_statement:ib\|present_state~9" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "washer_statement:ib\|present_state~8 " "Info: Encoded state bit washer_statement:ib\|present_state~8" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "washer_statement:ib\|present_state~7 " "Info: Encoded state bit washer_statement:ib\|present_state~7" {  } {  } 0}  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|washer\|washer_statement:ib\|present_state.ready 000 " "Info: State \|washer\|washer_statement:ib\|present_state.ready uses code string 000" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 15 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|washer\|washer_statement:ib\|present_state.wash1 001 " "Info: State \|washer\|washer_statement:ib\|present_state.wash1 uses code string 001" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 15 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|washer\|washer_statement:ib\|present_state.wash2 101 " "Info: State \|washer\|washer_statement:ib\|present_state.wash2 uses code string 101" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 15 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|washer\|washer_statement:ib\|present_state.wash3 010 " "Info: State \|washer\|washer_statement:ib\|present_state.wash3 uses code string 010" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 15 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|washer\|washer_statement:ib\|present_state.wash4 011 " "Info: State \|washer\|washer_statement:ib\|present_state.wash4 uses code string 011" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "14 " "Info: Ignored 14 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "14 " "Info: Ignored 14 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "washer_statement:ib\|s~2 washer_statement:ib\|process2~1 " "Info: Duplicate register washer_statement:ib\|s~2 merged to single register washer_statement:ib\|process2~1" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "washer_statement:ib\|s~0 washer_statement:ib\|process2~1 " "Info: Duplicate register washer_statement:ib\|s~0 merged to single register washer_statement:ib\|process2~1" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 49 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[5\] VCC " "Warning: Pin seg\[5\] stuck at VCC" {  } { { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[4\] VCC " "Warning: Pin seg\[4\] stuck at VCC" {  } { { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[3\] VCC " "Warning: Pin seg\[3\] stuck at VCC" {  } { { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 12 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "132 " "Info: Implemented 132 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "25 " "Info: Implemented 25 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "81 " "Info: Implemented 81 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "22 " "Info: Implemented 22 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 09 13:58:11 2006 " "Info: Processing ended: Thu Nov 09 13:58:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0}  } {  } 0}