washer.map.qmsg

用VHDL编的洗衣机程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 09 13:57:58 2006 " "Info: Processing started: Thu Nov 09 13:57:58 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off washer -c washer " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off washer -c washer" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "washer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file washer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 washer-washer_1 " "Info: Found design unit 1: washer-washer_1" {  } { { "D:/washer/washer.vhd" "washer-washer_1" "" { Text "D:/washer/washer.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 washer " "Info: Found entity 1: washer" {  } { { "D:/washer/washer.vhd" "washer" "" { Text "D:/washer/washer.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7-seg7_1 " "Info: Found design unit 1: seg7-seg7_1" {  } { { "D:/washer/seg7.vhd" "seg7-seg7_1" "" { Text "D:/washer/seg7.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7 " "Info: Found entity 1: seg7" {  } { { "D:/washer/seg7.vhd" "seg7" "" { Text "D:/washer/seg7.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "modelctrl.vhd 2 1 " "Info: Using design file modelctrl.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 modelctrl-modelctrl_1 " "Info: Found design unit 1: modelctrl-modelctrl_1" {  } { { "D:/washer/modelctrl.vhd" "modelctrl-modelctrl_1" "" { Text "D:/washer/modelctrl.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 modelctrl " "Info: Found entity 1: modelctrl" {  } { { "D:/washer/modelctrl.vhd" "modelctrl" "" { Text "D:/washer/modelctrl.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "washer_statement.vhd 2 1 " "Info: Using design file washer_statement.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 washer_statement-washer_statement_1 " "Info: Found design unit 1: washer_statement-washer_statement_1" {  } { { "D:/washer/washer_statement.vhd" "washer_statement-washer_statement_1" "" { Text "D:/washer/washer_statement.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 washer_statement " "Info: Found entity 1: washer_statement" {  } { { "D:/washer/washer_statement.vhd" "washer_statement" "" { Text "D:/washer/washer_statement.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "statectrl washer_statement.vhd(22) " "Warning: VHDL Process Statement warning at washer_statement.vhd(22): signal statectrl is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "statectrl washer_statement.vhd(23) " "Warning: VHDL Process Statement warning at washer_statement.vhd(23): signal statectrl is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "statectrl washer_statement.vhd(24) " "Warning: VHDL Process Statement warning at washer_statement.vhd(24): signal statectrl is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "statectrl washer_statement.vhd(27) " "Warning: VHDL Process Statement warning at washer_statement.vhd(27): signal statectrl is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "statectrl washer_statement.vhd(28) " "Warning: VHDL Process Statement warning at washer_statement.vhd(28): signal statectrl is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 28 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "statectrl washer_statement.vhd(31) " "Warning: VHDL Process Statement warning at washer_statement.vhd(31): signal statectrl is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 31 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "washer_statement.vhd(36) " "Info: VHDL Case Statement information at washer_statement.vhd(36): OTHERS choice is never selected" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "power_w washer_statement.vhd(52) " "Warning: VHDL Process Statement warning at washer_statement.vhd(52): signal power_w is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 52 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "washer_statement.vhd(87) " "Info: VHDL Case Statement information at washer_statement.vhd(87): OTHERS choice is never selected" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 87 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s washer_statement.vhd(89) " "Warning: VHDL Process Statement warning at washer_statement.vhd(89): signal s is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 89 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "s washer_statement.vhd(49) " "Warning: VHDL Process Statement warning at washer_statement.vhd(49): signal or variable s may not be assigned a new value in every possible path through the Process Statement. Signal or variable s holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 49 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "div.vhd 2 1 " "Info: Using design file div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-div_1 " "Info: Found design unit 1: div-div_1" {  } { { "D:/washer/div.vhd" "div-div_1" "" { Text "D:/washer/div.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "D:/washer/div.vhd" "div" "" { Text "D:/washer/div.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "y1 div.vhd(25) " "Warning: VHDL Process Statement warning at div.vhd(25): signal y1 is in statement, but is not in sensitivity list" {  } { { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "y2 div.vhd(39) " "Warning: VHDL Process Statement warning at div.vhd(39): signal y2 is in statement, but is not in sensitivity list" {  } { { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 39 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "counter.vhd 2 1 " "Info: Using design file counter.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter_1 " "Info: Found design unit 1: counter-counter_1" {  } { { "D:/washer/counter.vhd" "counter-counter_1" "" { Text "D:/washer/counter.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "D:/washer/counter.vhd" "counter" "" { Text "D:/washer/counter.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count_1 counter.vhd(19) " "Warning: VHDL Process Statement warning at counter.vhd(19): signal count_1 is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count_1 counter.vhd(36) " "Warning: VHDL Process Statement warning at counter.vhd(36): signal count_1 is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 36 0 0 } }  } 0}