washer.tan.qmsg

用VHDL编的洗衣机程序

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk clk1000out div:ic\|y1 8.000 ns register " "Info: Minimum tco from clock clk to destination pin clk1000out through register div:ic\|y1 is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns div:ic\|y1 2 REG LC107 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC107; Fanout = 9; REG Node = 'div:ic\|y1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "0.000 ns" { clk div:ic|y1 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "3.000 ns" { clk div:ic|y1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div:ic\|y1 1 REG LC107 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC107; Fanout = 9; REG Node = 'div:ic\|y1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { div:ic|y1 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns clk1000out 2 PIN PIN_69 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'clk1000out'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "4.000 ns" { div:ic|y1 clk1000out } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "4.000 ns" { div:ic|y1 clk1000out } "NODE_NAME" } } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "3.000 ns" { clk div:ic|y1 } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "4.000 ns" { div:ic|y1 clk1000out } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "power seg\[0\] 15.000 ns Shortest " "Info: Shortest tpd from source pin power to destination pin seg\[0\] is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns power 1 PIN PIN_54 18 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 18; PIN Node = 'power'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { power } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns seg7:ie\|process1~64 2 COMB LC49 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC49; Fanout = 1; COMB Node = 'seg7:ie\|process1~64'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { power seg7:ie|process1~64 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns seg\[0\] 3 PIN PIN_41 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'seg\[0\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "4.000 ns" { seg7:ie|process1~64 seg[0] } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 86.67 % " "Info: Total cell delay = 13.000 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.33 % " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "15.000 ns" { power seg7:ie|process1~64 seg[0] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 09 13:58:22 2006 " "Info: Processing ended: Thu Nov 09 13:58:22 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}