washer.tan.qmsg

用VHDL编的洗衣机程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "s_and_p register washer_statement:ib\|process2~1 register washer_statement:ib\|process2~1 32.26 MHz 31.0 ns Internal " "Info: Clock s_and_p has Internal fmax of 32.26 MHz between source register washer_statement:ib\|process2~1 and destination register washer_statement:ib\|process2~1 (period= 31.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "26.000 ns + Longest register register " "Info: + Longest register to register delay is 26.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns washer_statement:ib\|process2~1 1 REG LC109 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC109; Fanout = 1; REG Node = 'washer_statement:ib\|process2~1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns washer_statement:ib\|process2~5 2 COMB LC39 2 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC39; Fanout = 2; COMB Node = 'washer_statement:ib\|process2~5'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { washer_statement:ib|process2~1 washer_statement:ib|process2~5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 18.000 ns washer_statement:ib\|s~19 3 COMB LC33 29 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 18.000 ns; Loc. = LC33; Fanout = 29; COMB Node = 'washer_statement:ib\|s~19'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { washer_statement:ib|process2~5 washer_statement:ib|s~19 } "NODE_NAME" } } } { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 26.000 ns washer_statement:ib\|process2~1 4 REG LC109 1 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 26.000 ns; Loc. = LC109; Fanout = 1; REG Node = 'washer_statement:ib\|process2~1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { washer_statement:ib|s~19 washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "20.000 ns 76.92 % " "Info: Total cell delay = 20.000 ns ( 76.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 23.08 % " "Info: Total interconnect delay = 6.000 ns ( 23.08 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "26.000 ns" { washer_statement:ib|process2~1 washer_statement:ib|process2~5 washer_statement:ib|s~19 washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "s_and_p destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock s_and_p to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns s_and_p 1 CLK PIN_1 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 2; CLK Node = 's_and_p'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { s_and_p } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns washer_statement:ib\|process2~1 2 REG LC109 1 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC109; Fanout = 1; REG Node = 'washer_statement:ib\|process2~1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "7.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "s_and_p source 10.000 ns - Longest register " "Info: - Longest clock path from clock s_and_p to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns s_and_p 1 CLK PIN_1 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 2; CLK Node = 's_and_p'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { s_and_p } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns washer_statement:ib\|process2~1 2 REG LC109 1 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC109; Fanout = 1; REG Node = 'washer_statement:ib\|process2~1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "7.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "26.000 ns" { washer_statement:ib|process2~1 washer_statement:ib|process2~5 washer_statement:ib|s~19 washer_statement:ib|process2~1 } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "washer_statement:ib\|process2~1 s_and_p s_and_p 22.000 ns register " "Info: tsu for register washer_statement:ib\|process2~1 (data pin = s_and_p, clock pin = s_and_p) is 22.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.000 ns + Longest pin register " "Info: + Longest pin to register delay is 28.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns s_and_p 1 CLK PIN_1 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 2; CLK Node = 's_and_p'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { s_and_p } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns washer_statement:ib\|process2~5 2 COMB LC39 2 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC39; Fanout = 2; COMB Node = 'washer_statement:ib\|process2~5'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { s_and_p washer_statement:ib|process2~5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns washer_statement:ib\|s~19 3 COMB LC33 29 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC33; Fanout = 29; COMB Node = 'washer_statement:ib\|s~19'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { washer_statement:ib|process2~5 washer_statement:ib|s~19 } "NODE_NAME" } } } { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 28.000 ns washer_statement:ib\|process2~1 4 REG LC109 1 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 28.000 ns; Loc. = LC109; Fanout = 1; REG Node = 'washer_statement:ib\|process2~1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { washer_statement:ib|s~19 washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.000 ns 82.14 % " "Info: Total cell delay = 23.000 ns ( 82.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 17.86 % " "Info: Total interconnect delay = 5.000 ns ( 17.86 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "28.000 ns" { s_and_p washer_statement:ib|process2~5 washer_statement:ib|s~19 washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "s_and_p destination 10.000 ns - Shortest register " "Info: - Shortest clock path from clock s_and_p to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns s_and_p 1 CLK PIN_1 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 2; CLK Node = 's_and_p'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { s_and_p } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns washer_statement:ib\|process2~1 2 REG LC109 1 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC109; Fanout = 1; REG Node = 'washer_statement:ib\|process2~1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "7.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "28.000 ns" { s_and_p washer_statement:ib|process2~5 washer_statement:ib|s~19 washer_statement:ib|process2~1 } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { s_and_p washer_statement:ib|process2~1 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk number\[5\] counter:id\|count_1\[3\] 55.000 ns register " "Info: tco from clock clk to destination pin number\[5\] through register counter:id\|count_1\[3\] is 55.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 21.000 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns div:ic\|y1 2 REG LC107 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC107; Fanout = 9; REG Node = 'div:ic\|y1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "1.000 ns" { clk div:ic|y1 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns div:ic\|y2 3 REG LC80 10 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC80; Fanout = 10; REG Node = 'div:ic\|y2'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { div:ic|y1 div:ic|y2 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns counter:id\|count_1\[3\] 4 REG LC35 114 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC35; Fanout = 114; REG Node = 'counter:id\|count_1\[3\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { div:ic|y2 counter:id|count_1[3] } "NODE_NAME" } } } { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns 80.95 % " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 19.05 % " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "21.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|count_1[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "33.000 ns + Longest register pin " "Info: + Longest register to pin delay is 33.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:id\|count_1\[3\] 1 REG LC35 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 114; REG Node = 'counter:id\|count_1\[3\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { counter:id|count_1[3] } "NODE_NAME" } } } { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns seg7:ie\|process1~130 2 COMB SEXP78 20 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP78; Fanout = 20; COMB Node = 'seg7:ie\|process1~130'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { counter:id|count_1[3] seg7:ie|process1~130 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 16.000 ns seg7:ie\|process1~223 3 COMB LC69 1 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC69; Fanout = 1; COMB Node = 'seg7:ie\|process1~223'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "6.000 ns" { seg7:ie|process1~130 seg7:ie|process1~223 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 17.000 ns seg7:ie\|process1~229 4 COMB LC70 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 17.000 ns; Loc. = LC70; Fanout = 1; COMB Node = 'seg7:ie\|process1~229'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "1.000 ns" { seg7:ie|process1~223 seg7:ie|process1~229 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 18.000 ns seg7:ie\|process1~235 5 COMB LC71 1 " "Info: 5: + IC(0.000 ns) + CELL(1.000 ns) = 18.000 ns; Loc. = LC71; Fanout = 1; COMB Node = 'seg7:ie\|process1~235'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "1.000 ns" { seg7:ie|process1~229 seg7:ie|process1~235 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 20.000 ns seg7:ie\|process1~58 6 COMB LC72 2 " "Info: 6: + IC(0.000 ns) + CELL(2.000 ns) = 20.000 ns; Loc. = LC72; Fanout = 2; COMB Node = 'seg7:ie\|process1~58'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "2.000 ns" { seg7:ie|process1~235 seg7:ie|process1~58 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 29.000 ns seg7:ie\|num\[5\]~8540 7 COMB LC27 3 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 29.000 ns; Loc. = LC27; Fanout = 3; COMB Node = 'seg7:ie\|num\[5\]~8540'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { seg7:ie|process1~58 seg7:ie|num[5]~8540 } "NODE_NAME" } } } { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 33.000 ns number\[5\] 8 PIN PIN_16 0 " "Info: 8: + IC(0.000 ns) + CELL(4.000 ns) = 33.000 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'number\[5\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "4.000 ns" { seg7:ie|num[5]~8540 number[5] } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "29.000 ns 87.88 % " "Info: Total cell delay = 29.000 ns ( 87.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 12.12 % " "Info: Total interconnect delay = 4.000 ns ( 12.12 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "33.000 ns" { counter:id|count_1[3] seg7:ie|process1~130 seg7:ie|process1~223 seg7:ie|process1~229 seg7:ie|process1~235 seg7:ie|process1~58 seg7:ie|num[5]~8540 number[5] } "NODE_NAME" } } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "21.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|count_1[3] } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "33.000 ns" { counter:id|count_1[3] seg7:ie|process1~130 seg7:ie|process1~223 seg7:ie|process1~229 seg7:ie|process1~235 seg7:ie|process1~58 seg7:ie|num[5]~8540 number[5] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "power number\[6\] 15.000 ns Longest " "Info: Longest tpd from source pin power to destination pin number\[6\] is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns power 1 PIN PIN_54 18 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 18; PIN Node = 'power'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { power } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns seg7:ie\|num\[6\]~8548 2 COMB LC25 3 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC25; Fanout = 3; COMB Node = 'seg7:ie\|num\[6\]~8548'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { power seg7:ie|num[6]~8548 } "NODE_NAME" } } } { "D:/washer/seg7.vhd" "" "" { Text "D:/washer/seg7.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns number\[6\] 3 PIN PIN_17 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'number\[6\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "4.000 ns" { seg7:ie|num[6]~8548 number[6] } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 86.67 % " "Info: Total cell delay = 13.000 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.33 % " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "15.000 ns" { power seg7:ie|num[6]~8548 number[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "counter:id\|nextsta_c s_and_p clk -3.000 ns register " "Info: th for register counter:id\|nextsta_c (data pin = s_and_p, clock pin = clk) is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 21.000 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns div:ic\|y1 2 REG LC107 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC107; Fanout = 9; REG Node = 'div:ic\|y1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "1.000 ns" { clk div:ic|y1 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns div:ic\|y2 3 REG LC80 10 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC80; Fanout = 10; REG Node = 'div:ic\|y2'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { div:ic|y1 div:ic|y2 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns counter:id\|nextsta_c 4 REG LC46 7 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC46; Fanout = 7; REG Node = 'counter:id\|nextsta_c'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { div:ic|y2 counter:id|nextsta_c } "NODE_NAME" } } } { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns 80.95 % " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 19.05 % " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "21.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|nextsta_c } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 28.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns s_and_p 1 CLK PIN_1 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 2; CLK Node = 's_and_p'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { s_and_p } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns washer_statement:ib\|process2~5 2 COMB LC39 2 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC39; Fanout = 2; COMB Node = 'washer_statement:ib\|process2~5'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { s_and_p washer_statement:ib|process2~5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns washer_statement:ib\|s~19 3 COMB LC33 29 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC33; Fanout = 29; COMB Node = 'washer_statement:ib\|s~19'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { washer_statement:ib|process2~5 washer_statement:ib|s~19 } "NODE_NAME" } } } { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 28.000 ns counter:id\|nextsta_c 4 REG LC46 7 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 28.000 ns; Loc. = LC46; Fanout = 7; REG Node = 'counter:id\|nextsta_c'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { washer_statement:ib|s~19 counter:id|nextsta_c } "NODE_NAME" } } } { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.000 ns 82.14 % " "Info: Total cell delay = 23.000 ns ( 82.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 17.86 % " "Info: Total interconnect delay = 5.000 ns ( 17.86 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "28.000 ns" { s_and_p washer_statement:ib|process2~5 washer_statement:ib|s~19 counter:id|nextsta_c } "NODE_NAME" } } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "21.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|nextsta_c } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "28.000 ns" { s_and_p washer_statement:ib|process2~5 washer_statement:ib|s~19 counter:id|nextsta_c } "NODE_NAME" } } }  } 0}