washer.tan.qmsg

用VHDL编的洗衣机程序

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family." {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "model " "Info: Assuming node model is an undefined clock" {  } { { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "model" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "s_and_p " "Info: Assuming node s_and_p is an undefined clock" {  } { { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "s_and_p" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div:ic\|y1 " "Info: Detected ripple clock div:ic\|y1 as buffer" {  } { { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 17 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "div:ic\|y1" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div:ic\|y2 " "Info: Detected ripple clock div:ic\|y2 as buffer" {  } { { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 31 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "div:ic\|y2" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter:id\|nextsta_c " "Info: Detected ripple clock counter:id\|nextsta_c as buffer" {  } { { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 8 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "counter:id\|nextsta_c" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "model register modelctrl:ia\|model1\[1\] register modelctrl:ia\|model1\[2\] 76.92 MHz 13.0 ns Internal " "Info: Clock model has Internal fmax of 76.92 MHz between source register modelctrl:ia\|model1\[1\] and destination register modelctrl:ia\|model1\[2\] (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns modelctrl:ia\|model1\[1\] 1 REG LC94 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC94; Fanout = 36; REG Node = 'modelctrl:ia\|model1\[1\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { modelctrl:ia|model1[1] } "NODE_NAME" } } } { "D:/washer/modelctrl.vhd" "" "" { Text "D:/washer/modelctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns modelctrl:ia\|model1\[2\] 2 REG LC95 39 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC95; Fanout = 39; REG Node = 'modelctrl:ia\|model1\[2\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { modelctrl:ia|model1[1] modelctrl:ia|model1[2] } "NODE_NAME" } } } { "D:/washer/modelctrl.vhd" "" "" { Text "D:/washer/modelctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { modelctrl:ia|model1[1] modelctrl:ia|model1[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "model destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock model to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns model 1 CLK PIN_84 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 3; CLK Node = 'model'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { model } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns modelctrl:ia\|model1\[2\] 2 REG LC95 39 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC95; Fanout = 39; REG Node = 'modelctrl:ia\|model1\[2\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "7.000 ns" { model modelctrl:ia|model1[2] } "NODE_NAME" } } } { "D:/washer/modelctrl.vhd" "" "" { Text "D:/washer/modelctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { model modelctrl:ia|model1[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "model source 10.000 ns - Longest register " "Info: - Longest clock path from clock model to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns model 1 CLK PIN_84 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 3; CLK Node = 'model'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { model } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns modelctrl:ia\|model1\[1\] 2 REG LC94 36 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 36; REG Node = 'modelctrl:ia\|model1\[1\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "7.000 ns" { model modelctrl:ia|model1[1] } "NODE_NAME" } } } { "D:/washer/modelctrl.vhd" "" "" { Text "D:/washer/modelctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { model modelctrl:ia|model1[1] } "NODE_NAME" } } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { model modelctrl:ia|model1[2] } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { model modelctrl:ia|model1[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/washer/modelctrl.vhd" "" "" { Text "D:/washer/modelctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/washer/modelctrl.vhd" "" "" { Text "D:/washer/modelctrl.vhd" 17 -1 0 } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { modelctrl:ia|model1[1] modelctrl:ia|model1[2] } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { model modelctrl:ia|model1[2] } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "10.000 ns" { model modelctrl:ia|model1[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register washer_statement:ib\|present_state~8 register counter:id\|count_1\[4\] 20.0 MHz 50.0 ns Internal " "Info: Clock clk has Internal fmax of 20.0 MHz between source register washer_statement:ib\|present_state~8 and destination register counter:id\|count_1\[4\] (period= 50.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "36.000 ns + Longest register register " "Info: + Longest register to register delay is 36.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns washer_statement:ib\|present_state~8 1 REG LC42 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC42; Fanout = 25; REG Node = 'washer_statement:ib\|present_state~8'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { washer_statement:ib|present_state~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns washer_statement:ib\|Select~115 2 COMB LC48 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC48; Fanout = 1; COMB Node = 'washer_statement:ib\|Select~115'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { washer_statement:ib|present_state~8 washer_statement:ib|Select~115 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 18.000 ns washer_statement:ib\|process2~5 3 COMB LC39 2 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 18.000 ns; Loc. = LC39; Fanout = 2; COMB Node = 'washer_statement:ib\|process2~5'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { washer_statement:ib|Select~115 washer_statement:ib|process2~5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 27.000 ns washer_statement:ib\|s~19 4 COMB LC33 29 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 27.000 ns; Loc. = LC33; Fanout = 29; COMB Node = 'washer_statement:ib\|s~19'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { washer_statement:ib|process2~5 washer_statement:ib|s~19 } "NODE_NAME" } } } { "D:/数字电路实验/washer/washer_statement.vhd" "" "" { Text "D:/数字电路实验/washer/washer_statement.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 35.000 ns counter:id\|count_1\[4\]~807 5 COMB LC36 1 " "Info: 5: + IC(2.000 ns) + CELL(6.000 ns) = 35.000 ns; Loc. = LC36; Fanout = 1; COMB Node = 'counter:id\|count_1\[4\]~807'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { washer_statement:ib|s~19 counter:id|count_1[4]~807 } "NODE_NAME" } } } { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 36.000 ns counter:id\|count_1\[4\] 6 REG LC37 103 " "Info: 6: + IC(0.000 ns) + CELL(1.000 ns) = 36.000 ns; Loc. = LC37; Fanout = 103; REG Node = 'counter:id\|count_1\[4\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "1.000 ns" { counter:id|count_1[4]~807 counter:id|count_1[4] } "NODE_NAME" } } } { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "28.000 ns 77.78 % " "Info: Total cell delay = 28.000 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.000 ns 22.22 % " "Info: Total interconnect delay = 8.000 ns ( 22.22 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "36.000 ns" { washer_statement:ib|present_state~8 washer_statement:ib|Select~115 washer_statement:ib|process2~5 washer_statement:ib|s~19 counter:id|count_1[4]~807 counter:id|count_1[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.000 ns - Smallest " "Info: - Smallest clock skew is -9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 21.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns div:ic\|y1 2 REG LC107 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC107; Fanout = 9; REG Node = 'div:ic\|y1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "1.000 ns" { clk div:ic|y1 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns div:ic\|y2 3 REG LC80 10 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC80; Fanout = 10; REG Node = 'div:ic\|y2'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { div:ic|y1 div:ic|y2 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns counter:id\|count_1\[4\] 4 REG LC37 103 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC37; Fanout = 103; REG Node = 'counter:id\|count_1\[4\]'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { div:ic|y2 counter:id|count_1[4] } "NODE_NAME" } } } { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns 80.95 % " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 19.05 % " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "21.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|count_1[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 30.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 30.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/washer/washer.vhd" "" "" { Text "D:/washer/washer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns div:ic\|y1 2 REG LC107 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC107; Fanout = 9; REG Node = 'div:ic\|y1'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "1.000 ns" { clk div:ic|y1 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns div:ic\|y2 3 REG LC80 10 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC80; Fanout = 10; REG Node = 'div:ic\|y2'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { div:ic|y1 div:ic|y2 } "NODE_NAME" } } } { "D:/washer/div.vhd" "" "" { Text "D:/washer/div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns counter:id\|nextsta_c 4 REG LC46 7 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC46; Fanout = 7; REG Node = 'counter:id\|nextsta_c'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "9.000 ns" { div:ic|y2 counter:id|nextsta_c } "NODE_NAME" } } } { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 30.000 ns washer_statement:ib\|present_state~8 5 REG LC42 25 " "Info: 5: + IC(2.000 ns) + CELL(6.000 ns) = 30.000 ns; Loc. = LC42; Fanout = 25; REG Node = 'washer_statement:ib\|present_state~8'" {  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "8.000 ns" { counter:id|nextsta_c washer_statement:ib|present_state~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "24.000 ns 80.00 % " "Info: Total cell delay = 24.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 20.00 % " "Info: Total interconnect delay = 6.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "30.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|nextsta_c washer_statement:ib|present_state~8 } "NODE_NAME" } } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "21.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|count_1[4] } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "30.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|nextsta_c washer_statement:ib|present_state~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/数字电路实验/washer/counter.vhd" "" "" { Text "D:/数字电路实验/washer/counter.vhd" 21 -1 0 } }  } 0}  } { { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "36.000 ns" { washer_statement:ib|present_state~8 washer_statement:ib|Select~115 washer_statement:ib|process2~5 washer_statement:ib|s~19 counter:id|count_1[4]~807 counter:id|count_1[4] } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "21.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|count_1[4] } "NODE_NAME" } } } { "D:/washer/db/washer_cmp.qrpt" "" "" { Report "D:/washer/db/washer_cmp.qrpt" Compiler "washer" "UNKNOWN" "V1" "D:/washer/db/washer.quartus_db" { Floorplan "" "" "30.000 ns" { clk div:ic|y1 div:ic|y2 counter:id|nextsta_c washer_statement:ib|present_state~8 } "NODE_NAME" } } }  } 0}