washer.map.rpt

用VHDL编的洗衣机程序

; Analysis & Synthesis Resource Utilization by Entity                          ;
+----------------------------+------------+------+-----------------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name         ;
+----------------------------+------------+------+-----------------------------+
; |washer                    ; 81         ; 29   ; |washer                     ;
;    |counter:id|            ; 10         ; 0    ; |washer|counter:id          ;
;    |div:ic|                ; 12         ; 0    ; |washer|div:ic              ;
;    |modelctrl:ia|          ; 6          ; 0    ; |washer|modelctrl:ia        ;
;    |seg7:ie|               ; 41         ; 0    ; |washer|seg7:ie             ;
;    |washer_statement:ib|   ; 9          ; 0    ; |washer|washer_statement:ib ;
+----------------------------+------------+------+-----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/washer/washer.map.eqn.


+-------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                        ;
+-------------------------------------------------------------+-----------------+
; File Name                                                   ; Used in Netlist ;
+-------------------------------------------------------------+-----------------+
; washer.vhd                                                  ; yes             ;
; seg7.vhd                                                    ; yes             ;
; D:/washer/modelctrl.vhd                                     ; yes             ;
; D:/washer/washer_statement.vhd                              ; yes             ;
; D:/washer/div.vhd                                           ; yes             ;
; D:/washer/counter.vhd                                       ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.inc     ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.tdf     ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/altshift.tdf    ; yes             ;
+-------------------------------------------------------------+-----------------+


+----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary  ;
+----------------------+-----------------------+
; Resource             ; Usage                 ;
+----------------------+-----------------------+
; Logic cells          ; 81                    ;
; Total registers      ; 29                    ;
; I/O pins             ; 29                    ;
; Shareable expanders  ; 22                    ;
; Parallel expanders   ; 23                    ;
; Maximum fan-out node ; counter:id|count_1[2] ;
; Maximum fan-out      ; 46                    ;
; Total fan-out        ; 620                   ;
; Average fan-out      ; 4.70                  ;
+----------------------+-----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu Nov 09 13:57:58 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off washer -c washer
Info: Found 2 design units, including 1 entities, in source file washer.vhd
    Info: Found design unit 1: washer-washer_1
    Info: Found entity 1: washer
Info: Found 2 design units, including 1 entities, in source file seg7.vhd
    Info: Found design unit 1: seg7-seg7_1
    Info: Found entity 1: seg7
Info: Using design file modelctrl.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: modelctrl-modelctrl_1
    Info: Found entity 1: modelctrl
Info: Using design file washer_statement.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: washer_statement-washer_statement_1
    Info: Found entity 1: washer_statement
Warning: VHDL Process Statement warning at washer_statement.vhd(22): signal statectrl is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at washer_statement.vhd(23): signal statectrl is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at washer_statement.vhd(24): signal statectrl is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at washer_statement.vhd(27): signal statectrl is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at washer_statement.vhd(28): signal statectrl is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at washer_statement.vhd(31): signal statectrl is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at washer_statement.vhd(36): OTHERS choice is never selected
Warning: VHDL Process Statement warning at washer_statement.vhd(52): signal power_w is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at washer_statement.vhd(87): OTHERS choice is never selected
Warning: VHDL Process Statement warning at washer_statement.vhd(89): signal s is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at washer_statement.vhd(49): signal or variable s may not be assigned a new value in every possible path through the Process Statement. Signal or variable s holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: div-div_1
    Info: Found entity 1: div
Warning: VHDL Process Statement warning at div.vhd(25): signal y1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at div.vhd(39): signal y2 is in statement, but is not in sensitivity list
Info: Using design file counter.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter-counter_1
    Info: Found entity 1: counter
Warning: VHDL Process Statement warning at counter.vhd(19): signal count_1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at counter.vhd(36): signal count_1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at seg7.vhd(42): signal num1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at seg7.vhd(45): signal num2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at seg7.vhd(48): signal num3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at seg7.vhd(36): signal or variable seg may not be assigned a new value in every possible path through the Process Statement. Signal or variable seg holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at seg7.vhd(36): signal or variable num may not be assigned a new value in every possible path through the Process Statement. Signal or variable num holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: LATCH primitive seg7:ie|seg[3] is permanently enabled
Warning: LATCH primitive seg7:ie|seg[2] is permanently enabled
Warning: LATCH primitive seg7:ie|seg[1] is permanently enabled
Warning: LATCH primitive seg7:ie|seg[0] is permanently enabled
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine |washer|washer_statement:ib|present_state contains 5 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |washer|washer_statement:ib|present_state
Info: Encoding result for state machine |washer|washer_statement:ib|present_state
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit washer_statement:ib|present_state~9
        Info: Encoded state bit washer_statement:ib|present_state~8
        Info: Encoded state bit washer_statement:ib|present_state~7
    Info: State |washer|washer_statement:ib|present_state.ready uses code string 000
    Info: State |washer|washer_statement:ib|present_state.wash1 uses code string 001
    Info: State |washer|washer_statement:ib|present_state.wash2 uses code string 101
    Info: State |washer|washer_statement:ib|present_state.wash3 uses code string 010
    Info: State |washer|washer_statement:ib|present_state.wash4 uses code string 011
Info: Ignored 14 buffer(s)
    Info: Ignored 14 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register washer_statement:ib|s~2 merged to single register washer_statement:ib|process2~1
    Info: Duplicate register washer_statement:ib|s~0 merged to single register washer_statement:ib|process2~1
Warning: Output pins are stuck at VCC or GND
    Warning: Pin seg[5] stuck at VCC
    Warning: Pin seg[4] stuck at VCC
    Warning: Pin seg[3] stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin clk to global clock signal
Info: Implemented 132 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 25 output pins
    Info: Implemented 81 macrocells
    Info: Implemented 22 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 26 warnings
    Info: Processing ended: Thu Nov 09 13:58:11 2006
    Info: Elapsed time: 00:00:12