main.vhd

一个有效位为4位的十进制的数字频率计,VHDL语言编写

--
--  File: main.vhd
--  主文件，将各模块组合起来，
--  reset:复位，clk1K:1KHZ时钟，
--  col:LED位选，led:LED数据  

library IEEE;
use IEEE.std_logic_1164.all;

entity main is
	port (
		reset: in STD_LOGIC;
		clk1: in STD_LOGIC;
		freq: in STD_LOGIC;
		led1: out STD_LOGIC_VECTOR(3 downto 0);
		led2: out STD_LOGIC_VECTOR(3 downto 0);
		led3: out STD_LOGIC_VECTOR(3 downto 0);
		led4: out STD_LOGIC_VECTOR(3 downto 0)
	);
end main;


architecture rtl of main is	 

component fdiv is  	
	port ( 	    
		clkin: in STD_LOGIC;
		clkout: out STD_LOGIC
	);
end component fdiv;	

component counter is
	port (
		clk: in STD_LOGIC;
		clkclr: in STD_LOGIC;
		on_off: in STD_LOGIC;
		clr: in STD_LOGIC;			
		cary: out STD_LOGIC;
		value: out INTEGER range 0 to 9
	);
end component counter;

component latcher is
	port (
		clk: in STD_LOGIC;
		d: in INTEGER range 0 to 9;
		q: out INTEGER range 0 to 9
	);
end component latcher;	

component display is
	port ( 	
		data1: in INTEGER range 0 to 9;
		data2: in INTEGER range 0 to 9;
		data3: in INTEGER range 0 to 9;
		data4: in INTEGER range 0 to 9;
		overflow:in STD_LOGIC;
		led1: out STD_LOGIC_VECTOR(3 downto 0);
		led2: out STD_LOGIC_VECTOR(3 downto 0);
		led3: out STD_LOGIC_VECTOR(3 downto 0);
		led4: out STD_LOGIC_VECTOR(3 downto 0)		
	);
end component display;

signal clk05,gate,overflow:std_logic;
signal clk2,clk3,clk4:std_logic;
signal num1,num2,num3,num4:integer range 0 to 9;
signal dat1,dat2,dat3,dat4:integer range 0 to 9;
begin 
	p0:	fdiv    port map(clkin=>clk1,clkout=>clk05);
	p1:	counter port map(clk=>freq,clkclr=>clk1,on_off=>clk05,clr=>reset,cary=>clk2,value=>num1);
	p2:	counter port map(clk=>clk2,clkclr=>clk1,on_off=>clk05,clr=>reset,cary=>clk3,value=>num2);
	p3:	counter port map(clk=>clk3,clkclr=>clk1,on_off=>clk05,clr=>reset,cary=>clk4,value=>num3);
	p4:	counter port map(clk=>clk4,clkclr=>clk1,on_off=>clk05,clr=>reset,cary=>overflow,value=>num4); 
   pp1: latcher port map(clk=>clk05,d=>num1,q=>dat1);
   pp2: latcher port map(clk=>clk05,d=>num2,q=>dat2);
   pp3: latcher port map(clk=>clk05,d=>num3,q=>dat3);
   pp4: latcher port map(clk=>clk05,d=>num4,q=>dat4);
   d1:	display port map(data1=>dat1,data2=>dat2,data3=>dat3,data4=>dat4,overflow=>overflow,
                         led1=>led1,led2=>led2,led3=>led3,led4=>led4);

end rtl;