top.vhd

Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and prese

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity toprafa is 
	port (
	 S_filx :out std_logic_vector (5 downto 0);
	 S_colx :out std_logic_vector (5 downto 0);
	 c_filx :out std_logic_vector (5 downto 0);
	 c_colx :out std_logic_vector (5 downto 0);
	 mldirx :out std_logic_vector (14 downto 0);
	 s_lecturax :out std_logic;
	 s_lecturasx :out std_logic;
	 fuerax :out std_logic;
	 encontadorx :out std_logic ;
	 encntx:out std_logic;
	 encompx:out std_logic;
	 enmultiplicax:out std_logic;
	 fincomparax:out std_logic;
	 finalmacenax:out std_logic;
	 fin_totalx:out std_logic;
	 resultadox :out std_logic ;

	
--------------------------------------------------------------
--------------------------------------------------------------	
	Dir_lec: out STD_LOGIC_VECTOR(14 downto 0);
	Dir_alm: out STD_LOGIC_VECTOR(14 downto 0);
	Dat_lec: in STD_LOGIC_VECTOR(7 downto 0);
	Dat_alm: out STD_LOGIC_VECTOR(7 downto 0);
	Enable_lec: out std_logic;
	Enable_alm: out std_logic;
	--datos: inout STD_LOGIC_VECTOR(7 downto 0);
	--direc: inout STD_LOGIC_VECTOR(14 downto 0);
	clk: in std_logic;
	async_reset: in std_logic;
	--sync_reset: in std_logic;
	enable_gen: in std_logic;
	csl: out std_logic;
	wel: out std_logic;
	oel: out std_logic;
	csa: out std_logic;
	wea: out std_logic;
	oea: out std_logic;
	finfinal: out std_logic
	--fin1: out std_logic; -- Puerto adicional para poder mirar el fin del contador1.
	--fin2: out std_logic  -- Puerto adicional para poder mirar el fin del contador2.	
	);
end toprafa;

architecture rafaelin of toprafa is

component contador is
generic (
nb_width : integer:=6;
nb_lenght: integer:=6;
width : integer:= 64;
lenght: integer:= 64
);
    port (
        enable: in STD_LOGIC;
        --sinc_reset: in STD_LOGIC;
        asinc_reset: in STD_LOGIC;
        clk: in STD_LOGIC;
        fil : out STD_LOGIC_VECTOR(nb_width-1 downto 0);
        col : out STD_LOGIC_VECTOR(nb_lenght-1 downto 0)
    );
end component;

component cnt is

generic (nb_width : integer:=6;
nb_length: integer:=6;
width : integer:= 63;
lenght: integer:= 63
);

    port (
        enable_cnt: in STD_LOGIC;
        asinc_reset: in STD_LOGIC;
        i : in STD_LOGIC_VECTOR(nb_width-1 downto 0);
        j : in STD_LOGIC_VECTOR(nb_length-1 downto 0);
        fila : out STD_LOGIC_VECTOR(nb_width-1 downto 0);
        columna : out STD_LOGIC_VECTOR(nb_length-1 downto 0);
    	desborde:out STD_LOGIC
    );
    
end component;

component lectura is

generic (
		dir_long : integer :=14
);


 port (
        enable: in STD_LOGIC;
        asinc_reset: in STD_LOGIC;
        clk : in STD_LOGIC;
	dir : in STD_LOGIC_VECTOR(dir_long downto 0);
	bus_a : out STD_LOGIC_VECTOR(dir_long downto 0);
	bus_d : in STD_LOGIC_VECTOR(7 downto 0);
	fin : out STD_LOGIC;
	Fin_lectura: out STD_logic;
	Fuera_matriz: in STD_logic;
        S0 : out std_logic_vector(7 downto 0);
        S1 : out std_logic_vector(7 downto 0);
        S2 : out std_logic_vector(7 downto 0);
        S3 : out std_logic_vector(7 downto 0);
        S4 : out std_logic_vector(7 downto 0);
        S5 : out std_logic_vector(7 downto 0);
        S6 : out std_logic_vector(7 downto 0);
        S7 : out std_logic_vector(7 downto 0);
        S8 : out std_logic_vector(7 downto 0);
	cs : out STD_LOGIC;
	we : out STD_LOGIC;
	oe : out STD_LOGIC
   		 );

end component;

component multycomp is

generic (
G0 : integer :=1;
G1 : integer :=1;			-- matriz de sobel
G2 : integer :=1;
G3 :integer :=0;
G4 :integer :=0;
G5 : integer :=0;
G6 :integer  :=-1;
G7 : integer :=-1;
G8 : integer :=-1;
valorlimite: integer :=128
);

 port (
        enable: in STD_LOGIC;
        asinc_reset: in STD_LOGIC;
        clk: in STD_LOGIC;
	fin :out std_logic;
	resultado: out std_logic;				--fin del modulo lectura
        S0 : in std_logic_vector(7 downto 0);
        S1 : in std_logic_vector(7 downto 0);
        S2 : in std_logic_vector(7 downto 0);
        S3 : in std_logic_vector(7 downto 0);
        S4 : in std_logic_vector(7 downto 0);
        S5 : in std_logic_vector(7 downto 0);
        S6 : in std_logic_vector(7 downto 0);
        S7 : in std_logic_vector(7 downto 0);
        S8 : in std_logic_vector(7 downto 0));
end component;

component FSM is
    port (
        en_global: in STD_LOGIC;
	desborde: in std_logic; -- Senal del bloque cnt cuando el pixel a computar esta fuera de la matriz;
	ini_cuenta1: out STD_LOGIC;
        ini_cuenta2: out STD_LOGIC; -- Senal utilizada a modo de reloj para el bloque cnt;
        ini_compara: out STD_LOGIC;
	fin_compara: in STD_LOGIC;
	ini_lectura : out std_logic;
        fin_lectura: in std_logic;
	fin_lecturas: in std_logic;
        ini_almacena: out STD_LOGIC;
        fin_almacena: in STD_LOGIC;
        ini_multiplica: out STD_LOGIC;
        fin_matriz: in STD_LOGIC; -- Lo da el ultimo bloque cuando escribe el ultimo pixel de la matriz de bordes
        Fin: out STD_LOGIC;
        Clk: in STD_LOGIC;
        reset: in STD_LOGIC
    );
end component;


component almacena is
	generic (
	         ancho_dir :  integer := 15;   	
	         ancho_dat :  integer :=8	
	        );
	        	
	port (
	      bus_a : out std_logic_vector (ancho_dir-1 downto 0);
	      bus_d : out std_logic_vector (ancho_dat-1 downto 0);
	      cs : out std_logic;
	      oe : out std_logic;
	      we : out std_logic;
	      resul: in std_logic;
	      clk : in std_logic;
	      reset: in std_logic;
	      enable: in std_logic;
	      fin: out std_logic;
	      finmatriz: out std_logic
	);
	
end component;

component multiplica is

generic (nb_width : integer:=6;
nb_length: integer:=6;
width : integer:= 64;
length: integer:= 64;
dir_long : integer :=15
);

port (
        enable: in STD_LOGIC;
        asinc_reset: in STD_LOGIC;
        clk: in STD_LOGIC;
        fil : in STD_LOGIC_VECTOR(nb_width-1 downto 0);
        col : in STD_LOGIC_VECTOR(nb_length-1 downto 0);
	dir : out STD_LOGIC_VECTOR(dir_long-1 downto 0)
    );

end component;


signal S_fil : std_logic_vector (5 downto 0);
signal S_col : std_logic_vector (5 downto 0);
signal c_fil : std_logic_vector (5 downto 0);
signal c_col : std_logic_vector (5 downto 0);
signal mldir : std_logic_vector (14 downto 0);
signal s_lectura : std_logic;
signal s_lecturas : std_logic;
signal fuera : std_logic;
signal encontador : std_logic ;
signal encnt: std_logic;
signal encomp: std_logic;
signal enmultiplica: std_logic;
signal enalmacena: std_logic;
signal enlectura: std_logic;
signal finlectura: std_logic;
signal fincompara: std_logic;
signal finalmacena: std_logic;
signal fin_total: std_logic;
signal finfsm : std_logic ;
signal direccion : std_logic_vector (14 downto 0);
signal datos_signal : std_logic_vector (7 downto 0);
signal resultado : std_logic ;
signal S0 : std_logic_vector(7 downto 0);
signal S1 : std_logic_vector(7 downto 0);
signal S2 : std_logic_vector(7 downto 0);
signal S3 : std_logic_vector(7 downto 0);
signal S4 : std_logic_vector(7 downto 0);
signal S5 : std_logic_vector(7 downto 0);
signal S6 : std_logic_vector(7 downto 0);
signal S7 : std_logic_vector(7 downto 0);
signal S8 : std_logic_vector(7 downto 0);

signal cs1, cs2, we1, we2, oe1, oe2: std_logic;
signal datos1, datos2:  STD_LOGIC_VECTOR(7 downto 0);
signal direc1, direc2: STD_LOGIC_VECTOR(14 downto 0);
begin

bloqueuno: contador
	generic map (6,6,64,64) 
	port map (enable => encontador,asinc_reset => async_reset,
	clk => clk, fil => S_fil,col => S_col);

bloquedos: cnt
	generic map(6,6,63,63) 
	port map (enable_cnt => encnt, asinc_reset => async_reset,
	i => S_fil,j => S_col,fila => c_fil, columna=> c_col, desborde=>fuera);

bloquetres: multiplica
	generic map(6,6,64,64,15) 
	port map (enable => enmultiplica,asinc_reset => async_reset,
	clk => clk, fil => c_fil, col => c_col,dir => mldir);

bloquecuatro: lectura 
	generic map(14)
	port map (enable => enlectura, asinc_reset => async_reset, clk => clk,fuera_matriz =>fuera,
	dir => mldir,
	bus_a => Dir_lec,
	bus_d => Dat_lec,
	fin => s_lecturas,fin_lectura=>s_lectura, 
	S0 => S0, S1 => S1, S2 => S2, S3 => S3, S4 => S4, S5 => S5, S6 => S6, S7 => S7,
	S8 => S8, cs => csl, we => wel, oe =>oel);

bloquecinco : multycomp 
	generic map(1,1,1,0,0,0,-1,-1,-1,128)
	port map (enable => encomp, asinc_reset => async_reset, clk => clk, 
	fin => fincompara, resultado => resultado, s0 => S0,s1 => S1,s2 => S2,s3 => S3,
	s4 => S4,s5 => S5,s6 => S6,s7 => S7,s8 => S8);  

bloqueseis : almacena 
	generic map(15,8)
	port map (bus_a => Dir_alm,bus_D => Dat_alm, cs =>csa ,oe =>oea ,we =>wea,
	resul =>resultado ,clk =>clk ,reset => async_reset ,enable => enalmacena ,
	fin =>finalmacena ,finmatriz =>fin_total);

bloquefsm: fsm 
	port map (En_global => enable_gen, ini_cuenta1=>encontador,ini_cuenta2=>encnt,desborde=>fuera,
	ini_multiplica=>enmultiplica,ini_lectura=>enlectura,fin_lecturas=>s_lecturas,
	fin_lectura=>s_lectura,ini_compara=>encomp, fin_compara=>fincompara, ini_almacena=>enalmacena,
	fin_almacena=>finalmacena, fin_matriz => fin_total, fin=>finfinal,Clk => clk, reset => async_reset);
	
	
	 Enable_lec <= enlectura;
	 Enable_alm <= enalmacena;
	 S_filx <= s_fil;
	 S_colx <= s_col;
	 c_filx <= c_fil;
	 c_colx <= c_col;
	 mldirx <= mldir;
	 s_lecturax <= s_lectura;
	 s_lecturasx <= s_lecturas;
	 fuerax <= fuera;
	 encontadorx <= encontador ;
	 encntx <= encnt;
	 encompx <= encomp;
	 enmultiplicax<= enmultiplica;
	 fincomparax <= fincompara;
	 finalmacenax <= finalmacena;
	 fin_totalx <= fin_total;
	 resultadox <=resultado ;
	 


end rafaelin;