mult.vhd

Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and prese

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;

entity multiplica is

generic (nb_width : integer:=6;
nb_length: integer:=6;
width : integer:= 64;
length: integer:= 64;
dir_long : integer :=15
);


 port (
        enable: in STD_LOGIC;
        asinc_reset: in STD_LOGIC;
        clk: in STD_LOGIC;
        fil : in STD_LOGIC_VECTOR(nb_width-1 downto 0);
        col : in STD_LOGIC_VECTOR(nb_length-1 downto 0);
	dir : out STD_LOGIC_VECTOR(dir_long-1 downto 0)
    );

end multiplica;

architecture multiplica_arch of multiplica is

signal aux_dir : std_logic_vector(dir_long-1 downto 0);
signal aux_sdir : std_logic_vector(dir_long-1 downto 0);


begin

	comb: process(enable, fil, col,aux_sdir)
	--variable vwidth: std_logic_vector(nb_width-1 downto 0);
	variable mult: std_logic_vector(dir_long-1 downto 0);
	begin
	        --vwidth := conv_std_logic_vector(width,nb_width);
	        mult := (others => '0');
                if (enable ='1') then
			--if ((fil < 0) or (col < 0) or (col > width-1) or (fil > length-1)) then
			--	aux_dir <= (others=>'1');        -- Asignamos un valor sin sentido .
				
			--else
				mult(dir_long-1 downto 6) := "000" & fil; 
				mult(5 downto 0):= "000000"; 		--* vwidth;Se  puede hacer directamente con un shift, pues multiplicamos por 64;
				aux_dir <= mult + col;	
			--end if;
		else 
		   aux_dir <= aux_sdir;
		end if;
	end process;

	sinc : process(asinc_reset, clk,aux_dir)
	begin
		if(asinc_reset ='1') then
                        aux_sdir <= (others => '0');
		elsif (clk'event and clk ='1') then
			aux_sdir <= aux_dir;
		end if;
	end process;

	dir <= aux_sdir;

end multiplica_arch;