contador.vhd

Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and prese

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity contador is

generic (nb_width : integer:=6;
nb_lenght: integer:=6;
width : integer:= 64;
lenght: integer:= 64
);

    port (
        enable: in STD_LOGIC;
        asinc_reset: in STD_LOGIC;
        clk: in STD_LOGIC;
        fil : out STD_LOGIC_VECTOR(nb_width-1 downto 0);
        col : out STD_LOGIC_VECTOR(nb_lenght-1 downto 0)
    );
end contador;

architecture contador_arch of contador is

signal cuenta_col : std_logic_vector(nb_width-1 downto 0);
signal cuenta_fil : std_logic_vector(nb_lenght-1 downto 0);
signal aux_fil : std_logic_vector(nb_lenght-1 downto 0);
signal aux_col : std_logic_vector(nb_width-1 downto 0);

begin
  	comb : process(enable, cuenta_col, cuenta_fil)
  	begin
  	
  		
		if (enable ='1') then
		         if (cuenta_col < width-1) then 		
			    aux_col <= cuenta_col+'1';
			    aux_fil <= cuenta_fil;
			
			 else
				aux_col <= (others => '0');
				if (cuenta_fil < lenght-1) then
					aux_fil <= cuenta_fil +'1';
					
				else
					aux_fil <= (others => '0');
		
				end if;
					
			 end if;
		else
			aux_col <= cuenta_col;
			aux_fil <= cuenta_fil;
		end if;
	end process;
	
	sinc : process (asinc_reset, clk,aux_fil,aux_col) 
	begin
		if (asinc_reset ='1') then
		
			cuenta_fil <= (others => '0');		
			cuenta_col <= (others => '0');
				
		
		elsif (clk'event and clk ='1') then
			
			cuenta_fil <= aux_fil;
			cuenta_col <= aux_col;
		end if;
		
	end process; 	
	fil <= cuenta_fil;
	col <= cuenta_col;		
end contador_arch;