top_total.vhd

Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and prese

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity toptotal is 
	port (
	
	clk: in std_logic;
	async_reset: in std_logic;
	bus_dir :out STD_LOGIC_VECTOR(14 downto 0);
	bus_dat :inout STD_LOGIC_VECTOR(7 downto 0);
	cs: out std_logic;
	we: out std_logic;
	oe: out std_logic;
	rgb : out std_logic_vector(5 downto 0);
	sync_h : out std_logic;
	sync_v : out std_logic
	);
	
end toptotal;

architecture top_filtro of toptotal is

component toprafa is
port (

	Dir_lec: out STD_LOGIC_VECTOR(14 downto 0);
	Dir_alm: out STD_LOGIC_VECTOR(14 downto 0);
	Dat_lec: in STD_LOGIC_VECTOR(7 downto 0);
	Dat_alm: out STD_LOGIC_VECTOR(7 downto 0);
	Enable_lec: out std_logic;
	Enable_alm: out std_logic;
	clk: in std_logic;
	async_reset: in std_logic;
	enable_gen: in std_logic;
	csl: out std_logic;
	wel: out std_logic;
	oel: out std_logic;
	csa: out std_logic;
	wea: out std_logic;
	oea: out std_logic;
	finfinal: out std_logic	
	);
end component;

component pantalla2 is

	port (
		reset: in std_logic;	-- se馻l de reset as韓crono
		clk: in std_logic;		-- se馻l de reloj digital
-- se馻l que da permiso a esta entidad para acceder a los buses de la
-- RAM y mostrar la imagen en pantalla
		enable: in std_logic;
-- se馻l que pone en funcionamiento los contadores que se utilizan para
-- generar las se馻les de sincronismo y posicionamiento de la imagen
		ena: in std_logic;	
		bus_dat: in std_logic_vector (7 downto 0);  -- bus de datos
		bus_dir: out std_logic_vector (14 downto 0);-- bus direcciones
		cs: out std_logic;	-- l韓eas de control de RAM
		oe: out std_logic;
		we: out std_logic;
		rgb: out std_logic_vector (5 downto 0);	-- se馻l VGA de salida
		sinch: out std_logic;	-- se馻l de sincronismo horizontal
		sincv: out std_logic	-- se馻l de sinc. vertical
	);
end component;

type state_values is (reposo, procesa, screen);
signal estado_actual, estado_futuro : state_values;
signal enable_procesa, enable_pantalla1, enable_pantalla2 : std_logic;
signal enable_lectura, enable_almacena : std_logic;
signal data1_bus, data2_bus, data3_bus, datao_bus : std_logic_vector(7 downto 0);
signal address1_bus, address2_bus, address3_bus, addresso_bus : std_logic_vector (14 downto 0);
signal cs1, cs2, cs3, cso : std_logic;
signal we1, we2, we3, weo : std_logic;
signal oe1, oe2, oe3, oeo : std_logic;
signal fin_procesa,async_reset1 : std_logic;

begin

bloqueuno: toprafa

	port map(
			Dir_lec => address1_bus,
			Dir_alm => address2_bus,
			Dat_lec => data1_bus,
			Dat_alm => data2_bus,
			Enable_lec => enable_lectura,
			Enable_alm => enable_almacena,
			clk => clk,
			async_reset => async_reset1,
			enable_gen => enable_procesa,
			csl => cs1, 
			wel => we1,
			oel => oe1,
			csa => cs2,
			wea => we2,
			oea => oe2,
			finfinal => fin_procesa);
bloquedos : pantalla2

	port map(

		reset => async_reset1, 
		clk => clk,
		enable => enable_pantalla2,
		ena =>	enable_pantalla1,
		bus_dat => data3_bus,
		bus_dir => address3_bus,
		cs => cs3,
		oe => oe3,
		we => we3,
		rgb => rgb,
		sinch => sync_h,
		sincv => sync_v);

combinacional : process(estado_actual, fin_procesa,async_reset1)
		begin
		
		
			case estado_actual is
			
			when reposo =>
			
				enable_procesa <= '0';
				enable_pantalla1 <= '0';
				enable_pantalla2 <= '0';
				if(async_reset1 = '1') then
					estado_futuro <= reposo;
				else
					estado_futuro <= procesa;			
				end if;

			when procesa =>
			
				enable_pantalla1 <= '1';
				enable_pantalla2 <= '0';
				
				if (fin_procesa = '0') then
					enable_procesa <= '1';
					estado_futuro <= procesa;
				else
					enable_procesa <= '0';
					estado_futuro <= screen;
 				end if;
					estado_futuro <= screen;
 			
 			when screen =>
 			
 				enable_pantalla1 <= '1';
				enable_pantalla2 <= '1';
				enable_procesa <= '0';
				estado_futuro <= screen;
			
			end case;
end process;

sincronismo : process(clk,estado_futuro, async_reset1)
	
begin
    	if(async_reset1 = '1') then
      		estado_actual <= reposo;
      	elsif(clk'event and clk ='1') then
      		estado_actual <= estado_futuro;
        end if;
        
end process sincronismo;

--dummy : process(enable_lectura, oe1,oe2,oe3,enable_almacena, enable_pantalla2, cs1, cs2, cs3, we1, we2, we3, address1_bus, address2_bus, address3_bus, bus_dat, data2_bus) 
--begin
        bus_dat <= data2_bus when enable_almacena ='1' else
        	   (others =>'Z');
        data1_bus <= bus_dat;
        data3_bus <= bus_dat;
        
	--tao_bus <= data1_bus when enable_lectura ='1' else (others =>'Z');
	--tao_bus <= data2_bus when enable_almacena ='1' else (others =>'Z');
	--tao_bus <= data3_bus when enable_pantalla2 ='1' else (others =>'Z');

	bus_dir <= address1_bus when enable_lectura  ='1' else
		   address2_bus when enable_almacena ='1' else
	  	   address3_bus;
	
	--addresso_bus <= address1_bus when enable_lectura  ='1' else (others =>'Z');
	--addresso_bus <= address2_bus when enable_almacena ='1' else (others =>'Z');
	--addresso_bus <= address3_bus when enable_pantalla ='1' else (others =>'Z');

	cs <= '0' when (cs1 = '0' or cs2 = '0' or cs3 = '0') else '1';
	--cso <= cs1 when enable_lectura  ='1' else 'Z';
	--cso <= cs2 when enable_almacena  ='1' else 'Z';
	--cso <= cs3 when enable_pantalla  ='1' else 'Z';

        we <= '0' when  (we1 = '0' or we2 = '0' or we3 = '0')else '1';
	--weo <= we1 when enable_lectura  ='1' else 'z';
	--weo <= we2 when enable_almacena  ='1' else 'z';
	--weo <= we3 when enable_pantalla  ='1' else 'z';
	
	oe <= '0' when (oe1 = '0' or oe2 = '0' or oe3 = '0') else '1';
	--oeo <= oe1 when enable_lectura  ='1' else 'z';
	--oeo <= oe2 when enable_almacena  ='1' else 'z';
	--oeo <= oe3 when enable_pantalla  ='1' else 'z';

--end process;
async_reset1<= not async_reset;
end top_filtro;