design_top_tb.tf

XILINX的FPGA实现的双口ram源码

	rd_clk = 1'b0;
	// --------------------
	#100 // Time=8600 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=8700 ns
	rd_en = 1'b1;
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=8800 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=8900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=9000 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=9100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=9200 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=9300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=9400 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=9500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=9600 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=9700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=9800 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=9900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=10000 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=10100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=10200 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=10300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=10400 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=10500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=10600 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=10700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=10800 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=10900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=11000 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=11100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=11200 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=11300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=11400 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=11500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=11600 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=11700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=11800 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=11900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=12000 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=12100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=12200 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=12300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=12400 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=12500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=12600 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=12700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=12800 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=12900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=13000 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=13100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=13200 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=13300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=13400 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=13500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=13600 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=13700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=13800 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=13900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=14000 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=14100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=14200 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=14300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=14400 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=14500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=14600 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#200 // Time=14800 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=15000 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=15200 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=15400 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=15600 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=15800 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=16000 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=16200 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=16400 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=16600 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=16800 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=17000 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=17200 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=17400 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=17600 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=17800 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=18000 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=18200 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=18400 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=18600 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=18800 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=19000 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=19200 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=19400 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=19600 ns
	wr_clk = 1'b1;
	// --------------------
	#200 // Time=19800 ns
	wr_clk = 1'b0;
	// --------------------
	#200 // Time=20000 ns
	// --------------------

	if (TX_ERROR == 0) begin
		$display("No errors or warnings");
		$fdisplay(TX_FILE,"No errors or warnings");
	end else begin
		$display("%d errors found in simulation",TX_ERROR);
		$fdisplay(TX_FILE,"%d errors found in simulation",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task CHECK_dout;
	input [15:0] NEXT_dout;

	#0 begin
		if (NEXT_dout !== dout) begin
			$display("Error at time=%dns dout=%b, expected=%b",
				$time, dout, NEXT_dout);
			$fdisplay(TX_FILE,"Error at time=%dns dout=%b, expected=%b",
				$time, dout, NEXT_dout);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_full;
	input NEXT_full;

	#0 begin
		if (NEXT_full !== full) begin
			$display("Error at time=%dns full=%b, expected=%b",
				$time, full, NEXT_full);
			$fdisplay(TX_FILE,"Error at time=%dns full=%b, expected=%b",
				$time, full, NEXT_full);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_empty;
	input NEXT_empty;

	#0 begin
		if (NEXT_empty !== empty) begin
			$display("Error at time=%dns empty=%b, expected=%b",
				$time, empty, NEXT_empty);
			$fdisplay(TX_FILE,"Error at time=%dns empty=%b, expected=%b",
				$time, empty, NEXT_empty);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_almost_full;
	input NEXT_almost_full;

	#0 begin
		if (NEXT_almost_full !== almost_full) begin
			$display("Error at time=%dns almost_full=%b, expected=%b",
				$time, almost_full, NEXT_almost_full);
			$fdisplay(TX_FILE,"Error at time=%dns almost_full=%b, expected=%b",
				$time, almost_full, NEXT_almost_full);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_almost_empty;
	input NEXT_almost_empty;

	#0 begin
		if (NEXT_almost_empty !== almost_empty) begin
			$display("Error at time=%dns almost_empty=%b, expected=%b",
				$time, almost_empty, NEXT_almost_empty);
			$fdisplay(TX_FILE,"Error at time=%dns almost_empty=%b, expected=%b",
				$time, almost_empty, NEXT_almost_empty);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_wr_count;
	input [1:0] NEXT_wr_count;

	#0 begin
		if (NEXT_wr_count !== wr_count) begin
			$display("Error at time=%dns wr_count=%b, expected=%b",
				$time, wr_count, NEXT_wr_count);
			$fdisplay(TX_FILE,"Error at time=%dns wr_count=%b, expected=%b",
				$time, wr_count, NEXT_wr_count);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_rd_count;
	input [1:0] NEXT_rd_count;

	#0 begin
		if (NEXT_rd_count !== rd_count) begin
			$display("Error at time=%dns rd_count=%b, expected=%b",
				$time, rd_count, NEXT_rd_count);
			$fdisplay(TX_FILE,"Error at time=%dns rd_count=%b, expected=%b",
				$time, rd_count, NEXT_rd_count);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_rd_ack;
	input NEXT_rd_ack;

	#0 begin
		if (NEXT_rd_ack !== rd_ack) begin
			$display("Error at time=%dns rd_ack=%b, expected=%b",
				$time, rd_ack, NEXT_rd_ack);
			$fdisplay(TX_FILE,"Error at time=%dns rd_ack=%b, expected=%b",
				$time, rd_ack, NEXT_rd_ack);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_rd_err;
	input NEXT_rd_err;

	#0 begin
		if (NEXT_rd_err !== rd_err) begin
			$display("Error at time=%dns rd_err=%b, expected=%b",
				$time, rd_err, NEXT_rd_err);
			$fdisplay(TX_FILE,"Error at time=%dns rd_err=%b, expected=%b",
				$time, rd_err, NEXT_rd_err);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_wr_ack;
	input NEXT_wr_ack;

	#0 begin
		if (NEXT_wr_ack !== wr_ack) begin
			$display("Error at time=%dns wr_ack=%b, expected=%b",
				$time, wr_ack, NEXT_wr_ack);
			$fdisplay(TX_FILE,"Error at time=%dns wr_ack=%b, expected=%b",
				$time, wr_ack, NEXT_wr_ack);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_wr_err;
	input NEXT_wr_err;

	#0 begin
		if (NEXT_wr_err !== wr_err) begin
			$display("Error at time=%dns wr_err=%b, expected=%b",
				$time, wr_err, NEXT_wr_err);
			$fdisplay(TX_FILE,"Error at time=%dns wr_err=%b, expected=%b",
				$time, wr_err, NEXT_wr_err);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

endmodule