clkgen.v

来自「verilog 编写的pic16c5x时钟模块」· Verilog 代码 · 共 38 行

module clkgen(clk,reset,clk1,clk2,clk3,clk4);
    input clk,reset;
    output clk1,clk2,clk3,clk4;
    reg clk1,clk2,clk3,clk4; 
    reg  [2:0]	state;//状态寄存器
    
    parameter idle=3'b000,
       	      q1=3'b001,
		      q2=3'b010,
		      q3=3'b011,									   
		      q4=3'b100;
   
   always@(posedge clk)
       
	     if(!reset)
	       begin
		   state<=idle;clk1<=0; clk2<=0;clk3<=0; clk4<=0;
		  end
	     else
	        case(state)
	          idle:begin
			     state<=q1;clk1<=0; clk2<=0;clk3<=0; clk4<=0;
	            	end
			  q1:begin
			     state<=q2;clk1<=1; clk2<=0;clk3<=0; clk4<=0;
	            	end
			  q2:begin
			     state<=q3;clk1<=0; clk2<=1;clk3<=0; clk4<=0;
	            	end
			  q3:begin
			     state<=q4;clk1<=0; clk2<=0;clk3<=1; clk4<=0;
	            	end
			  q4:begin
			     state<=q1;clk1<=0; clk2<=0;clk3<=0; clk4<=1;
	            	end
		    endcase

endmodule