wave.ado

verilog 编写的pic16c5x时钟模块

source {C:/Xilinx/data/projnav/scripts/VsimStopServer.tcl}
initIPC 1200
-- Auto Generated by Project Navigator to simulate
-- HDL Bencher Annotated Test Bench
--
vlib work
onbreak {resume}
onerror {quit -code 99 -force}
onElabError {resume}
vlog  clkgen.v
vlog  wave.ant
vlog  "C:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver  -lib work wave glbl
run -all
quit -force