magnitude.v

Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A c

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module magnitude(
	clk,
	clken,
	aclr,
	vectorX,
	vectorY,
	magnitude
);

input	clk;
input   clken;
input   aclr;
input	[8:0] vectorX;
input	[8:0] vectorY;
output	[9:0] magnitude;


parameter IN_PREC = 20;
parameter OUT_PREC = 10;
parameter PIPELINE = "YES";


wire [19:0] squares_w;
wire [19:0] squares;
wire [9:0] magnitude_w;
reg [19:0] squares_pipe;
reg [9:0] magnitude_pipe;



square_number	b2v_inst(.clock0(clk),.dataa_0(vectorX),.dataa_1(vectorY),.datab_0(vectorX),.datab_1(vectorY),.result(squares_w[18:0]));
defparam b2v_inst.PIPELINE = PIPELINE;


root_pipeline_wrapper	b2v_inst2(.clk(clk),.clken(clken),.aclr(aclr),.rad(squares_pipe),.root(magnitude_w));
defparam	b2v_inst2.PREC = OUT_PREC;
defparam	b2v_inst2.WIDTH = IN_PREC;
defparam    b2v_inst2.PIPELINE = PIPELINE;


assign	squares_w[19] = 0;
assign	squares[19:0] = squares_w[19:0];
assign  magnitude = magnitude_pipe;

always @ (posedge clk or posedge aclr) 
begin
   if (aclr)
	  begin
         squares_pipe = 0;
	     magnitude_pipe = 0;
	  end
   else if (clken)
      begin
         squares_pipe = squares;
         magnitude_pipe = magnitude_w;
      end
   end
endmodule