fpq_sound.syr

数字钟的实现

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: fpq_sound.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : fpq_sound.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : fpq_sound
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : fpq_sound
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fpq_sound.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/dig_clk/FEN_SOUND.vhdl in Library work.
Architecture behavioral of Entity fpq_sound is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <fpq_sound> (Architecture <behavioral>).
WARNING:Xst:819 - e:/vhdl/dig_clk/FEN_SOUND.vhdl line 33: The following signals are missing in the process sensitivity list:
   y.
Entity <fpq_sound> analyzed. Unit <fpq_sound> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq_sound>.
    Related source file is e:/vhdl/dig_clk/FEN_SOUND.vhdl.
    Found 14-bit up counter for signal <count>.
    Found 1-bit register for signal <x>.
    Found 1-bit register for signal <y>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <fpq_sound> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 14-bit up counter                 : 1
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <fpq_sound> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fpq_sound, actual ratio is 1.
FlipFlop y has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fpq_sound.ngr
Top Level Output File Name         : fpq_sound
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 3

Macro Statistics :
# Registers                        : 3
#      1-bit register              : 2
#      14-bit register             : 1
# Adders/Subtractors               : 1
#      14-bit adder                : 1

Cell Usage :
# BELS                             : 48
#      GND                         : 1
#      LUT1                        : 15
#      LUT2                        : 1
#      LUT4                        : 3
#      LUT4_L                      : 1
#      MUXCY                       : 13
#      VCC                         : 1
#      XORCY                       : 13
# FlipFlops/Latches                : 17
#      FDE                         : 1
#      FDR                         : 16
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 2
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      19  out of    768     2%  
 Number of Slice Flip Flops:            17  out of   1536     1%  
 Number of 4 input LUTs:                20  out of   1536     1%  
 Number of bonded IOBs:                  2  out of     96     2%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
x:Q                                | NONE                   | 2     |
CLK                                | BUFGP                  | 15    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 7.740ns (Maximum Frequency: 129.199MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.193ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'x:Q'
Delay:               3.025ns (Levels of Logic = 0)
  Source:            y (FF)
  Destination:       y (FF)
  Source Clock:      x:Q rising
  Destination Clock: x:Q rising

  Data Path: y to y
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  y (y)
     FDR:R                     0.734          y
    ----------------------------------------
    Total                      3.025ns (1.819ns logic, 1.206ns route)
                                       (60.1% logic, 39.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               7.740ns (Levels of Logic = 2)
  Source:            count_6 (FF)
  Destination:       x (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: count_6 to x
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  count_6 (count_6)
     LUT2:I0->O            1   0.549   1.035  _n00013 (CHOICE46)
     LUT4:I0->O           15   0.549   2.430  _n000155 (_n0001)
     FDE:CE                    0.886          x
    ----------------------------------------
    Total                      7.740ns (3.069ns logic, 4.671ns route)
                                       (39.7% logic, 60.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'x:Q'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            y_1 (FF)
  Destination:       CP500 (PAD)
  Source Clock:      x:Q rising

  Data Path: y_1 to CP500
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  y_1 (y_1)
     OBUF:I->O                 4.668          CP500_OBUF (CP500)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              7.193ns (Levels of Logic = 1)
  Source:            x (FF)
  Destination:       CP1000 (PAD)
  Source Clock:      CLK rising

  Data Path: x to CP1000
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              4   1.085   1.440  x (x)
     OBUF:I->O                 4.668          CP1000_OBUF (CP1000)
    ----------------------------------------
    Total                      7.193ns (5.753ns logic, 1.440ns route)
                                       (80.0% logic, 20.0% route)

=========================================================================
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