__projnav.log

数字钟的实现

Analyzing Entity <hour> (Architecture <behavioral>).
Entity <hour> analyzed. Unit <hour> generated.

Analyzing Entity <min> (Architecture <behavioral>).
Entity <min> analyzed. Unit <min> generated.

Analyzing Entity <second> (Architecture <behavioral>).
Entity <second> analyzed. Unit <second> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <szq> (Architecture <behavioral>).
WARNING:Xst:819 - e:/vhdl/dig_clk/xzq6.vhdl line 24: The following signals are missing in the process sensitivity list:
   Q6, Q5, Q4, Q3, Q2, Q1.
Entity <szq> analyzed. Unit <szq> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <szq>.
    Related source file is e:/vhdl/dig_clk/xzq6.vhdl.
Unit <szq> synthesized.


Synthesizing Unit <ymq>.
    Related source file is e:/vhdl/dig_clk/YMQ.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <second>.
    Related source file is e:/vhdl/dig_clk/second.vhdl.
INFO:Xst:1799 - State 0110 is never reached in FSM <CNT1>.
INFO:Xst:1799 - State 0101 is never reached in FSM <CNT1>.
    Found finite state machine <FSM_0> for signal <CNT1>.
    -----------------------------------------------------------------------
    | States             | 1                                              |
    | Transitions        | 1                                              |
    | Inputs             | 0                                              |
    | Outputs            | 0                                              |
    | Clock              | CLK (rising_edge)                              |
    | Clock enable       | $n0003 (positive)                              |
    | Reset              | CLR (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <COUT>.
    Found 4-bit comparator less for signal <$n0010> created at line 32.
    Found 4-bit adder for signal <$n0015> created at line 34.
    Found 4-bit register for signal <CNT0>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <second> synthesized.


Synthesizing Unit <min>.
    Related source file is e:/vhdl/dig_clk/MIN.vhdl.
    Found 1-bit register for signal <COUT>.
    Found 4-bit comparator less for signal <$n0008> created at line 36.
    Found 4-bit comparator less for signal <$n0010> created at line 31.
    Found 4-bit adder for signal <$n0011> created at line 37.
    Found 4-bit adder for signal <$n0015> created at line 33.
    Found 4-bit register for signal <CNT0>.
    Found 4-bit register for signal <CNT1>.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <min> synthesized.


Synthesizing Unit <hour>.
    Related source file is e:/vhdl/dig_clk/HOUR.vhdl.
    Found 4-bit comparator less for signal <$n0005> created at line 30.
    Found 4-bit adder for signal <$n0011> created at line 32.
    Found 4-bit register for signal <CNT0>.
    Found 4-bit up counter for signal <CNT1>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <hour> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is e:/vhdl/dig_clk/FPQ2MS.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <fpq1s>.
    Related source file is e:/vhdl/dig_clk/FPQ1S.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <count>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1s> synthesized.


Synthesizing Unit <fpq_sound>.
    Related source file is e:/vhdl/dig_clk/FEN_SOUND.vhdl.
    Found 14-bit up counter for signal <count>.
    Found 1-bit register for signal <x>.
    Found 1-bit register for signal <y>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <fpq_sound> synthesized.


Synthesizing Unit <bskz>.
    Related source file is e:/vhdl/dig_clk/bskz.vhdl.
    Found 1-bit register for signal <cp500>.
    Found 1-bit register for signal <cp1000>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <bskz> synthesized.


Synthesizing Unit <s_6>.
    Related source file is e:/vhdl/dig_clk/S_6.vhdl.
    Found 3-bit up counter for signal <i>.
    Summary:
	inferred   1 Counter(s).
Unit <s_6> synthesized.


Synthesizing Unit <clock>.
    Related source file is e:/vhdl/dig_clk/clock.vhf.
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CNT1> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 4
 4-bit adder                       : 4
# Counters                         : 5
 4-bit up counter                  : 1
 14-bit up counter                 : 1
 24-bit up counter                 : 1
 15-bit up counter                 : 1
 3-bit up counter                  : 1
# Registers                        : 14
 1-bit register                    : 10
 4-bit register                    : 4
# Latches                          : 1
 7-bit latch                       : 1
# Comparators                      : 10
 24-bit comparator lessequal       : 2
 24-bit comparator greatequal      : 1
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
 4-bit comparator less             : 4
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <COUT> (without init value) is constant in block <second>.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <clock> ...

Optimizing unit <szq> ...

Optimizing unit <bskz> ...

Optimizing unit <hour> ...

Optimizing unit <min> ...

Optimizing unit <fpq_sound> ...

Optimizing unit <fpq1s> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <ymq> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <XLXI_1_cp500> (without init value) is constant in block <clock>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clock, actual ratio is 17.
FlipFlop clr_i_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     139  out of    768    18%  
 Number of Slice Flip Flops:            92  out of   1536     5%  
 Number of 4 input LUTs:               228  out of   1536    14%  
 Number of bonded IOBs:                 15  out of     96    15%  
 Number of TBUFs:                        2  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_2(XLXI_3_I3_0:O)              | NONE(*)(XLXI_6_COUT)   | 21    |
XLXI_10__n0001(XLXI_10__n00011:O)  | NONE(*)(XLXI_10_Q_6)   | 7     |
XLXN_39(XLXI_4_I3_0:O)             | NONE(*)(clr_i_1)       | 4     |
clk                                | BUFGP                  | 59    |
XLXI_2_x:Q                         | NONE                   | 1     |
-----------------------------------+------------------------+-------+
(*) These 3 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.541ns (Maximum Frequency: 104.811MHz)
   Minimum input arrival time before clock: 9.663ns
   Maximum output required time after clock: 10.253ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\dig_clk/_ngo -i -p
xc2s50-tq144-6 clock.ngc clock.ngd 

Reading NGO file "e:/vhdl/dig_clk/clock.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40164 kilobytes

Writing NGD file "clock.ngd" ...

Writing NGDBUILD log file "clock.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        83 out of  1,536    5%
  Number of 4 input LUTs:           146 out of  1,536    9%
Logic Distribution:
    Number of occupied Slices:                         131 out of    768   17%
    Number of Slices containing only related logic:    131 out of    131  100%
    Number of Slices containing unrelated logic:         0 out of    131    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          232 out of  1,536   15%
      Number used as logic:                       146
      Number used as a route-thru:                 86
   Number of bonded IOBs:            15 out of     92   16%
      IOB Flip Flops:                               1
      IOB Latches:                                  7
   Number of Tbufs:                   2 out of    832    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  2,183
Additional JTAG gate count for IOBs:  768
Peak Memory Usage:  60 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin