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HDL Synthesis ReportMacro Statistics# Counters : 1 14-bit up counter : 1# Registers : 2 1-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <fpq_sound> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block fpq_sound, actual ratio is 1.FlipFlop y has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 19 out of 768 2% Number of Slice Flip Flops: 17 out of 1536 1% Number of 4 input LUTs: 20 out of 1536 1% Number of bonded IOBs: 2 out of 96 2% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+x:Q | NONE | 2 |CLK | BUFGP | 15 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 7.740ns (Maximum Frequency: 129.199MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 7.193ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
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Started process "Create Schematic Symbol".WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file e:\vhdl\dig_clk/bskz.vhdl, automatic determination of correct order of compilation of files in project file pepExtractor.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.Compiling vhdl file e:\vhdl\dig_clk/bskz.vhdl in Library work.ERROR:HDLParsers:3313 - e:\vhdl\dig_clk/bskz.vhdl Line 30. Undefined symbol 'ssec'. Should it be: sec?ERROR:HDLParsers:1209 - e:\vhdl\dig_clk/bskz.vhdl Line 30. ssec: Undefined symbol (last report in this block)ERROR:HDLParsers:164 - e:\vhdl\dig_clk/bskz.vhdl Line 34. parse error, unexpected END, expecting SEMICOLONERROR:HDLParsers:164 - e:\vhdl\dig_clk/bskz.vhdl Line 36. parse error, unexpected PROCESS, expecting IFtdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
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Started process "Create Schematic Symbol".Compiling vhdl file e:/vhdl/dig_clk/bskz.vhdl in Library work.Entity <bskz> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
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Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file e:/vhdl/dig_clk/bskz.vhdl in Library work.Architecture behavioral of Entity bskz is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <bskz> (Architecture <behavioral>).Entity <bskz> analyzed. Unit <bskz> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <bskz>. Related source file is e:/vhdl/dig_clk/bskz.vhdl. Found 1-bit register for signal <cp500>. Found 1-bit register for signal <cp1000>. Summary: inferred 2 D-type flip-flop(s).Unit <bskz> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 2 1-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <bskz> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bskz, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 7 out of 768 0% Number of Slice Flip Flops: 2 out of 1536 0% Number of 4 input LUTs: 10 out of 1536 0% Number of bonded IOBs: 18 out of 96 18% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 2 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: 7.620ns Maximum output required time after clock: 6.788ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file e:/vhdl/dig_clk/xzq6.vhdl in Library work.Entity <SZQ> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Release 6.2i - sch2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
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Started process "View VHDL Functional Model".Release 6.2i - sch2vhdl G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.ERROR:DesignEntry:7 - Net "clr" has the same name as an instance.Error: Process "View VHDL Functional Model" did not complete.
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Started process "Create Schematic Symbol".Release 6.2i - sch2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View VHDL Functional Model".Release 6.2i - sch2vhdl G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file e:/vhdl/dig_clk/S_6.vhdl in Library work.Architecture behavioral of Entity s_6 is up to date.Compiling vhdl file e:/vhdl/dig_clk/bskz.vhdl in Library work.Architecture behavioral of Entity bskz is up to date.Compiling vhdl file e:/vhdl/dig_clk/FEN_SOUND.vhdl in Library work.Architecture behavioral of Entity fpq_sound is up to date.Compiling vhdl file e:/vhdl/dig_clk/FPQ1S.vhdl in Library work.Architecture behavioral of Entity fpq1s is up to date.Compiling vhdl file e:/vhdl/dig_clk/FPQ2MS.vhdl in Library work.Architecture behavioral of Entity fpq2ms is up to date.Compiling vhdl file e:/vhdl/dig_clk/HOUR.vhdl in Library work.Architecture behavioral of Entity hour is up to date.Compiling vhdl file e:/vhdl/dig_clk/MIN.vhdl in Library work.Architecture behavioral of Entity min is up to date.Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.Architecture behavioral of Entity second is up to date.Compiling vhdl file e:/vhdl/dig_clk/YMQ.vhdl in Library work.Architecture behavioral of Entity ymq is up to date.Compiling vhdl file e:/vhdl/dig_clk/xzq6.vhdl in Library work.Architecture behavioral of Entity szq is up to date.Compiling vhdl file e:/vhdl/dig_clk/clock.vhf in Library work.Entity <clock> (Architecture <BEHAVIORAL>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <clock> (Architecture <BEHAVIORAL>).Entity <clock> analyzed. Unit <clock> generated.Analyzing Entity <s_6> (Architecture <behavioral>).Entity <s_6> analyzed. Unit <s_6> generated.Analyzing Entity <bskz> (Architecture <behavioral>).Entity <bskz> analyzed. Unit <bskz> generated.Analyzing Entity <fpq_sound> (Architecture <behavioral>).WARNING:Xst:819 - e:/vhdl/dig_clk/FEN_SOUND.vhdl line 33: The following signals are missing in the process sensitivity list: y.Entity <fpq_sound> analyzed. Unit <fpq_sound> generated.Analyzing Entity <fpq1s> (Architecture <behavioral>).Entity <fpq1s> analyzed. Unit <fpq1s> generated.Analyzing Entity <fpq2ms> (Architecture <behavioral>).Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.⌨️ 快捷键说明
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