__projnav.log

数字钟的实现

---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       6  out of    768     0%  
 Number of Slice Flip Flops:             4  out of   1536     0%  
 Number of 4 input LUTs:                10  out of   1536     0%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.530ns (Maximum Frequency: 153.139MHz)
   Minimum input arrival time before clock: 4.686ns
   Maximum output required time after clock: 7.193ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/HOUR.vhdl in Library work.
ERROR:HDLParsers:410 - e:/vhdl/dig_clk/HOUR.vhdl Line 30. Variable 'CNT1' CNT1
   is at left hand side of signal assignment statement.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/HOUR.vhdl in Library work.
Entity <HOUR> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/dig_clk/HOUR.vhdl in Library work.
Architecture behavioral of Entity hour is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <hour> (Architecture <behavioral>).
Entity <hour> analyzed. Unit <hour> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <hour>.
    Related source file is e:/vhdl/dig_clk/HOUR.vhdl.
    Found 4-bit comparator less for signal <$n0005> created at line 30.
    Found 4-bit adder for signal <$n0011> created at line 32.
    Found 4-bit register for signal <CNT0>.
    Found 4-bit up counter for signal <CNT1>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <hour> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 4-bit adder                       : 1
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 1
 4-bit register                    : 1
# Comparators                      : 1
 4-bit comparator less             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <hour> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block hour, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      11  out of    768     1%  
 Number of Slice Flip Flops:             8  out of   1536     0%  
 Number of 4 input LUTs:                16  out of   1536     1%  
 Number of bonded IOBs:                 10  out of     96    10%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.056ns (Maximum Frequency: 124.131MHz)
   Minimum input arrival time before clock: 5.217ns
   Maximum output required time after clock: 7.661ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/FPQ1S.vhdl in Library work.
Entity <fpq1S> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/FPQ2MS.vhdl in Library work.
Entity <fpq2ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/SEL.vhdl in Library work.
Entity <SEL> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/S_6.vhdl in Library work.
Entity <S_6> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/YMQ.vhdl in Library work.
Entity <YMQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/FEN_SOUND.vhdl in Library work.
Entity <fpq_sound> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/dig_clk/FEN_SOUND.vhdl in Library work.
Architecture behavioral of Entity fpq_sound is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <fpq_sound> (Architecture <behavioral>).
WARNING:Xst:819 - e:/vhdl/dig_clk/FEN_SOUND.vhdl line 33: The following signals are missing in the process sensitivity list:
   y.
Entity <fpq_sound> analyzed. Unit <fpq_sound> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq_sound>.
    Related source file is e:/vhdl/dig_clk/FEN_SOUND.vhdl.
    Found 14-bit up counter for signal <count>.
    Found 1-bit register for signal <x>.
    Found 1-bit register for signal <y>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <fpq_sound> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================