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Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block second, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 3 out of 768 0% Number of Slice Flip Flops: 4 out of 1536 0% Number of 4 input LUTs: 6 out of 1536 0% Number of bonded IOBs: 11 out of 96 11% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLK | BUFGP | 4 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 5.292ns (Maximum Frequency: 188.964MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 7.085ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file e:\vhdl\dig_clk/MIN.vhdl, automatic determination of correct order of compilation of files in project file pepExtractor.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.Compiling vhdl file e:\vhdl\dig_clk/MIN.vhdl in Library work.ERROR:HDLParsers:164 - e:\vhdl\dig_clk/MIN.vhdl Line 46. parse error, unexpected PROCESS, expecting IFtdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file e:/vhdl/dig_clk/MIN.vhdl in Library work.Entity <MIN> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file e:/vhdl/dig_clk/MIN.vhdl in Library work.Architecture behavioral of Entity min is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <min> (Architecture <behavioral>).Entity <min> analyzed. Unit <min> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <min>. Related source file is e:/vhdl/dig_clk/MIN.vhdl. Found 1-bit register for signal <COUT>. Found 4-bit comparator less for signal <$n0008> created at line 36. Found 4-bit comparator less for signal <$n0010> created at line 31. Found 4-bit adder for signal <$n0011> created at line 37. Found 4-bit adder for signal <$n0015> created at line 33. Found 4-bit register for signal <CNT0>. Found 4-bit register for signal <CNT1>. Summary: inferred 9 D-type flip-flop(s). inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s).Unit <min> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 2 4-bit adder : 2# Registers : 3 1-bit register : 1 4-bit register : 2# Comparators : 2 4-bit comparator less : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <min> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block min, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 14 out of 768 1% Number of Slice Flip Flops: 9 out of 1536 0% Number of 4 input LUTs: 23 out of 1536 1% Number of bonded IOBs: 11 out of 96 11% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLK | BUFGP | 9 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 7.110ns (Maximum Frequency: 140.647MHz) Minimum input arrival time before clock: 6.738ns Maximum output required time after clock: 7.661ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.ERROR:HDLParsers:3402 - e:/vhdl/dig_clk/second.vhdl Line 28. Read symbol =, expecting <= or := tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.Entity <second> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.Architecture behavioral of Entity second is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <second> (Architecture <behavioral>).Entity <second> analyzed. Unit <second> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <second>. Related source file is e:/vhdl/dig_clk/second.vhdl.INFO:Xst:1799 - State 0110 is never reached in FSM <CNT1>.INFO:Xst:1799 - State 0101 is never reached in FSM <CNT1>. Found finite state machine <FSM_0> for signal <CNT1>. ----------------------------------------------------------------------- | States | 1 | | Transitions | 1 | | Inputs | 0 | | Outputs | 0 | | Clock | CLK (rising_edge) | | Clock enable | $n0003 (positive) | | Reset | CLR (positive) | | Reset type | asynchronous | | Reset State | 0000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <COUT>. Found 4-bit comparator less for signal <$n0010> created at line 32. Found 4-bit adder for signal <$n0015> created at line 34. Found 4-bit register for signal <CNT0>. Summary: inferred 1 Finite State Machine(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s).Unit <second> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <CNT1> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 1 4-bit adder : 1# Registers : 2 1-bit register : 1 4-bit register : 1# Comparators : 1 4-bit comparator less : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <COUT> (without init value) is constant in block <second>.Optimizing unit <second> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block second, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:⌨️ 快捷键说明
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