__projnav.log

数字钟的实现

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-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.
ERROR:HDLParsers:3313 - e:/vhdl/dig_clk/second.vhdl Line 21. Undefined symbol
   'EN'.  Should it be: oN or iN?
ERROR:HDLParsers:1209 - e:/vhdl/dig_clk/second.vhdl Line 21. EN: Undefined
   symbol (last report in this block)
ERROR:HDLParsers:410 - e:/vhdl/dig_clk/second.vhdl Line 32. Variable 'CNT0' CNT0
   is at left hand side of signal assignment statement.
ERROR:HDLParsers:164 - e:/vhdl/dig_clk/second.vhdl Line 36. parse error,
   unexpected SEMICOLON
ERROR:HDLParsers:800 - e:/vhdl/dig_clk/second.vhdl Line 37. Type of COUT is
   incompatible with type of 0000.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.
ERROR:HDLParsers:410 - e:/vhdl/dig_clk/second.vhdl Line 32. Variable 'CNT0' CNT0
   is at left hand side of signal assignment statement.
ERROR:HDLParsers:164 - e:/vhdl/dig_clk/second.vhdl Line 36. parse error,
   unexpected SEMICOLON
ERROR:HDLParsers:800 - e:/vhdl/dig_clk/second.vhdl Line 37. Type of COUT is
   incompatible with type of 0000.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.
ERROR:HDLParsers:164 - e:/vhdl/dig_clk/second.vhdl Line 36. parse error,
   unexpected SEMICOLON
ERROR:HDLParsers:800 - e:/vhdl/dig_clk/second.vhdl Line 37. Type of COUT is
   incompatible with type of 0000.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.
ERROR:HDLParsers:164 - e:/vhdl/dig_clk/second.vhdl Line 36. parse error,
   unexpected SEMICOLON
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.
Entity <SECOND> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.
Architecture behavioral of Entity second is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <second> (Architecture <behavioral>).
Entity <second> analyzed. Unit <second> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <second>.
    Related source file is e:/vhdl/dig_clk/second.vhdl.
WARNING:Xst:1778 - Inout <SECGE> is assigned but never used.
WARNING:Xst:1778 - Inout <SECSHI> is assigned but never used.
INFO:Xst:1799 - State 0110 is never reached in FSM <CNT1>.
INFO:Xst:1799 - State 0101 is never reached in FSM <CNT1>.
    Found finite state machine <FSM_0> for signal <CNT1>.
    -----------------------------------------------------------------------
    | States             | 1                                              |
    | Transitions        | 1                                              |
    | Inputs             | 0                                              |
    | Outputs            | 0                                              |
    | Clock              | CLK (rising_edge)                              |
    | Clock enable       | $n0002 (positive)                              |
    | Reset              | $n0003 (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <COUT>.
    Found 4-bit comparator less for signal <$n0011> created at line 33.
    Found 4-bit up counter for signal <CNT0>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <second> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CNT1> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 4-bit comparator less             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <COUT> (without init value) is constant in block <second>.

Optimizing unit <second> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block second, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       3  out of    768     0%  
 Number of Slice Flip Flops:             4  out of   1536     0%  
 Number of 4 input LUTs:                 6  out of   1536     0%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.292ns (Maximum Frequency: 188.964MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.085ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.
Entity <second> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work.
Architecture behavioral of Entity second is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <second> (Architecture <behavioral>).
Entity <second> analyzed. Unit <second> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <second>.
    Related source file is e:/vhdl/dig_clk/second.vhdl.
INFO:Xst:1799 - State 0110 is never reached in FSM <CNT1>.
INFO:Xst:1799 - State 0101 is never reached in FSM <CNT1>.
    Found finite state machine <FSM_0> for signal <CNT1>.
    -----------------------------------------------------------------------
    | States             | 1                                              |
    | Transitions        | 1                                              |
    | Inputs             | 0                                              |
    | Outputs            | 0                                              |
    | Clock              | CLK (rising_edge)                              |
    | Clock enable       | $n0002 (positive)                              |
    | Reset              | $n0003 (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <COUT>.
    Found 4-bit comparator less for signal <$n0011> created at line 33.
    Found 4-bit up counter for signal <CNT0>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <second> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CNT1> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 4-bit comparator less             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <COUT> (without init value) is constant in block <second>.

Optimizing unit <second> ...