digclk.syr

数字钟的实现

-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 7.459ns (Maximum Frequency: 134.073MHz)
   Minimum input arrival time before clock: 5.102ns
   Maximum output required time after clock: 8.626ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.579ns (frequency: 179.251MHz)
  Total number of paths / destination ports: 1876 / 120
-------------------------------------------------------------------------
Delay:               5.579ns (Levels of Logic = 8)
  Source:            XLXI_3/count_9 (FF)
  Destination:       XLXI_3/count_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_3/count_9 to XLXI_3/count_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   0.626   1.078  XLXI_3/count_9 (XLXI_3/count_9)
     LUT2_L:I0->LO         1   0.479   0.000  XLXI_3/_n0001_wg_sel (N51)
     MUXCY:S->O            1   0.435   0.000  XLXI_3/_n0001_wg_cy (XLXI_3/_n0001_wg_cy)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/_n0001_wg_cy_rn_0 (XLXI_3/_n0001_wg_cy1)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/_n0001_wg_cy_rn_1 (XLXI_3/_n0001_wg_cy2)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/_n0001_wg_cy_rn_2 (XLXI_3/_n0001_wg_cy3)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/_n0001_wg_cy_rn_3 (XLXI_3/_n0001_wg_cy4)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/_n0001_wg_cy_rn_4 (XLXI_3/_n0001_wg_cy5)
     MUXCY:CI->O          26   0.246   1.546  XLXI_3/_n0001_wg_cy_rn_5 (XLXI_3/_n0001_wg_cy6)
     FDR:R                     0.892          XLXI_3/count_0
    ----------------------------------------
    Total                      5.579ns (2.955ns logic, 2.624ns route)
                                       (53.0% logic, 47.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_2/x'
  Clock period: 2.263ns (frequency: 441.803MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.263ns (Levels of Logic = 0)
  Source:            XLXI_2/y (FF)
  Destination:       XLXI_2/y (FF)
  Source Clock:      XLXI_2/x rising
  Destination Clock: XLXI_2/x rising

  Data Path: XLXI_2/y to XLXI_2/y
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   0.745  XLXI_2/y (XLXI_2/y)
     FDR:R                     0.892          XLXI_2/y
    ----------------------------------------
    Total                      2.263ns (1.518ns logic, 0.745ns route)
                                       (67.1% logic, 32.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXN_171'
  Clock period: 5.833ns (frequency: 171.432MHz)
  Total number of paths / destination ports: 206 / 44
-------------------------------------------------------------------------
Delay:               5.833ns (Levels of Logic = 3)
  Source:            XLXI_19/COUT (FF)
  Destination:       XLXI_8/CNT1_0 (FF)
  Source Clock:      XLXN_171 rising
  Destination Clock: XLXN_171 rising

  Data Path: XLXI_19/COUT to XLXI_8/CNT1_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.626   0.745  XLXI_19/COUT (XLXI_19/COUT)
     OR2:I1->O             1   0.479   0.681  XLXI_37 (XLXN_61)
     AND2:I1->O            2   0.479   1.040  XLXI_35 (XLXN_64)
     LUT4:I0->O            4   0.479   0.779  XLXI_8/_n0015 (XLXI_8/_n0015)
     FDCE:CE                   0.524          XLXI_8/CNT1_0
    ----------------------------------------
    Total                      5.833ns (2.587ns logic, 3.246ns route)
                                       (44.3% logic, 55.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_38/Clk_Out1'
  Clock period: 7.459ns (frequency: 134.073MHz)
  Total number of paths / destination ports: 1000 / 35
-------------------------------------------------------------------------
Delay:               7.459ns (Levels of Logic = 11)
  Source:            XLXI_38/cnt1_2_1 (FF)
  Destination:       XLXI_38/LCD_Data_7 (FF)
  Source Clock:      XLXI_38/Clk_Out1 rising
  Destination Clock: XLXI_38/Clk_Out1 rising

  Data Path: XLXI_38/cnt1_2_1 to XLXI_38/LCD_Data_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              3   0.626   1.066  XLXI_38/cnt1_2_1 (XLXI_38/cnt1_2_1)
     LUT2_D:I0->O          2   0.479   0.768  XLXI_38/_n0021<1>1_SW0 (N722)
     LUT4:I3->O            1   0.479   0.704  XLXI_38/LCD1602__n0025<1>lut_SW0 (N770)
     LUT4_L:I3->LO         1   0.479   0.000  XLXI_38/LCD1602__n0025<1>lut (XLXI_38/N5)
     MUXCY:S->O            1   0.435   0.000  XLXI_38/LCD1602__n0025<1>cy (XLXI_38/LCD1602__n0025<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  XLXI_38/LCD1602__n0025<2>cy (XLXI_38/LCD1602__n0025<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  XLXI_38/LCD1602__n0025<3>cy (XLXI_38/LCD1602__n0025<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  XLXI_38/LCD1602__n0025<4>cy (XLXI_38/LCD1602__n0025<4>_cyo)
     MUXCY:CI->O           2   0.056   0.000  XLXI_38/LCD1602__n0025<5>cy (XLXI_38/LCD1602__n0025<5>_cyo)
     MUXCY:CI->O           0   0.056   0.000  XLXI_38/LCD1602__n0025<6>cy (XLXI_38/LCD1602__n0025<6>_cyo)
     XORCY:CI->O           1   0.786   0.704  XLXI_38/LCD1602__n0025<7>_xor (XLXI_38/_n0025<7>)
     LUT4_L:I3->LO         1   0.479   0.000  XLXI_38/_n0016<7>1 (XLXI_38/_n0016<7>)
     FDE:D                     0.176          XLXI_38/LCD_Data_7
    ----------------------------------------
    Total                      7.459ns (4.217ns logic, 3.242ns route)
                                       (56.5% logic, 43.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXN_171'
  Total number of paths / destination ports: 18 / 17
-------------------------------------------------------------------------
Offset:              5.102ns (Levels of Logic = 4)
  Source:            smin (PAD)
  Destination:       XLXI_7/COUT (FF)
  Destination Clock: XLXN_171 rising

  Data Path: smin to XLXI_7/COUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.681  smin_IBUF (smin_IBUF)
     AND2:I0->O            3   0.479   0.794  XLXI_36 (XLXN_30)
     LUT4_L:I3->LO         1   0.479   0.270  XLXI_7/_n000322 (XLXI_7/_n0003_map246)
     LUT4:I1->O            1   0.479   0.681  XLXI_7/_n000324 (XLXI_7/_n0003)
     FDE:CE                    0.524          XLXI_7/COUT
    ----------------------------------------
    Total                      5.102ns (2.676ns logic, 2.426ns route)
                                       (52.5% logic, 47.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_38/Clk_Out1'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              2.194ns (Levels of Logic = 1)
  Source:            rst (PAD)
  Destination:       XLXI_38/LCD_Data_0 (FF)
  Destination Clock: XLXI_38/Clk_Out1 rising

  Data Path: rst to XLXI_38/LCD_Data_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.715   0.955  rst_IBUF (rst_IBUF)
     FDE:CE                    0.524          XLXI_38/LCD_Data_6
    ----------------------------------------
    Total                      2.194ns (1.239ns logic, 0.955ns route)
                                       (56.5% logic, 43.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 4 / 2
-------------------------------------------------------------------------
Offset:              8.626ns (Levels of Logic = 3)
  Source:            XLXI_2/x (FF)
  Destination:       sound (PAD)
  Source Clock:      clk rising

  Data Path: XLXI_2/x to sound
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   0.626   0.771  XLXI_2/x (XLXI_2/x)
     OR2:I1->O             1   0.479   0.681  XLXI_27 (XLXN_38)
     AND2:I0->O            1   0.479   0.681  XLXI_28 (sound_OBUF)
     OBUF:I->O                 4.909          sound_OBUF (sound)
    ----------------------------------------
    Total                      8.626ns (6.493ns logic, 2.133ns route)
                                       (75.3% logic, 24.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2/x'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              8.600ns (Levels of Logic = 3)
  Source:            XLXI_2/y (FF)
  Destination:       sound (PAD)
  Source Clock:      XLXI_2/x rising

  Data Path: XLXI_2/y to sound
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   0.745  XLXI_2/y (XLXI_2/y)
     OR2:I1->O             1   0.479   0.681  XLXI_26 (XLXN_39)
     AND2:I1->O            1   0.479   0.681  XLXI_28 (sound_OBUF)
     OBUF:I->O                 4.909          sound_OBUF (sound)
    ----------------------------------------
    Total                      8.600ns (6.493ns logic, 2.107ns route)
                                       (75.5% logic, 24.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_38/Clk_Out1'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              6.216ns (Levels of Logic = 1)
  Source:            XLXI_38/LCD_RS (FF)
  Destination:       lcd_rs (PAD)
  Source Clock:      XLXI_38/Clk_Out1 rising

  Data Path: XLXI_38/LCD_RS to lcd_rs
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.626   0.681  XLXI_38/LCD_RS (XLXI_38/LCD_RS)
     OBUF:I->O                 4.909          lcd_rs_OBUF (lcd_rs)
    ----------------------------------------
    Total                      6.216ns (5.535ns logic, 0.681ns route)
                                       (89.0% logic, 11.0% route)

=========================================================================
CPU : 19.92 / 21.27 s | Elapsed : 20.00 / 21.00 s
 
--> 

Total memory usage is 116372 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   11 (   0 filtered)
Number of infos    :    4 (   0 filtered)