digclk.syr

数字钟的实现

	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <MIN> synthesized.


Synthesizing Unit <fpq1S>.
    Related source file is "F:/FPGA/VHDL/waitpast/dig_clk_lcd/FPQ1S.vhdl".
    Found 4x1-bit ROM for signal <$n0003>.
    Found 1-bit tristate buffer for signal <CP>.
    Found 26-bit comparator lessequal for signal <$n0002>.
    Found 26-bit comparator lessequal for signal <$n0005>.
    Found 26-bit comparator greatequal for signal <$n0007>.
    Found 26-bit comparator lessequal for signal <$n0008>.
    Found 26-bit up counter for signal <count>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1S> synthesized.


Synthesizing Unit <fpq_sound>.
    Related source file is "F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl".
    Found 16-bit up counter for signal <count>.
    Found 1-bit register for signal <x>.
    Found 1-bit register for signal <y>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <fpq_sound> synthesized.


Synthesizing Unit <bskz>.
    Related source file is "F:/FPGA/VHDL/waitpast/dig_clk_lcd/bskz.vhdl".
    Found 1-bit register for signal <cp500>.
    Found 1-bit register for signal <cp1000>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <bskz> synthesized.


Synthesizing Unit <digclk>.
    Related source file is "F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf".
Unit <digclk> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 4x1-bit ROM                                           : 1
# Adders/Subtractors                                   : 6
 4-bit adder                                           : 3
 5-bit adder                                           : 1
 8-bit adder                                           : 1
 8-bit addsub                                          : 1
# Counters                                             : 6
 15-bit up counter                                     : 1
 16-bit up counter                                     : 1
 26-bit up counter                                     : 1
 4-bit up counter                                      : 3
# Registers                                            : 15
 1-bit register                                        : 10
 4-bit register                                        : 3
 5-bit register                                        : 1
 8-bit register                                        : 1
# Comparators                                          : 12
 15-bit comparator less                                : 1
 26-bit comparator greatequal                          : 1
 26-bit comparator lessequal                           : 3
 4-bit comparator less                                 : 5
 5-bit comparator less                                 : 1
 5-bit comparator lessequal                            : 1
# Multiplexers                                         : 4
 4-bit 4-to-1 multiplexer                              : 3
 8-bit 31-to-1 multiplexer                             : 1
# Tristates                                            : 1
 1-bit tristate buffer                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <XLXI_38/Current_State> on signal <Current_State[1:3]> with gray encoding.
----------------------------
 State          | Encoding
----------------------------
 set_dlnf       | 000
 set_cursor     | 001
 set_dcb        | 011
 set_cgram      | 010
 write_cgram    | 110
 set_ddram      | 111
 write_lcd_data | 101
----------------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# ROMs                                                 : 1
 4x1-bit ROM                                           : 1
# Adders/Subtractors                                   : 6
 4-bit adder                                           : 3
 5-bit adder                                           : 1
 8-bit adder                                           : 1
 8-bit addsub                                          : 1
# Counters                                             : 6
 15-bit up counter                                     : 1
 16-bit up counter                                     : 1
 26-bit up counter                                     : 1
 4-bit up counter                                      : 3
# Registers                                            : 38
 Flip-Flops                                            : 38
# Comparators                                          : 12
 15-bit comparator less                                : 1
 26-bit comparator greatequal                          : 1
 26-bit comparator lessequal                           : 3
 4-bit comparator less                                 : 5
 5-bit comparator less                                 : 1
 5-bit comparator lessequal                            : 1
# Multiplexers                                         : 4
 4-bit 4-to-1 multiplexer                              : 3
 8-bit 31-to-1 multiplexer                             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1989 - Unit <fpq1S>: instances <Mcompar__n0002>, <Mcompar__n0005> of unit <LPM_COMPARE_7> are equivalent, second instance is removed
Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx.
WARNING:Xst:2041 - Unit digclk: 1 internal tristate is replaced by logic (pull-up yes): XLXN_17.

Optimizing unit <digclk> ...
WARNING:Xst:1710 - FF/Latch  <XLXI_19/CNT1_3> (without init value) has a constant value of 0 in block <digclk>.

Optimizing unit <LCD1602> ...

Optimizing unit <MIN> ...
WARNING:Xst:1710 - FF/Latch  <CNT1_3> (without init value) has a constant value of 0 in block <MIN>.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block digclk, actual ratio is 4.
FlipFlop XLXI_38/cnt1_0 has been replicated 4 time(s)
FlipFlop XLXI_38/cnt1_1 has been replicated 4 time(s)
FlipFlop XLXI_38/cnt1_2 has been replicated 3 time(s)
FlipFlop XLXI_38/cnt1_3 has been replicated 4 time(s)
FlipFlop XLXI_38/cnt1_4 has been replicated 3 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : digclk.ngr
Top Level Output File Name         : digclk
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 17

Cell Usage :
# BELS                             : 437
#      AND2                        : 3
#      GND                         : 1
#      INV                         : 22
#      LUT1                        : 60
#      LUT1_L                      : 6
#      LUT2                        : 9
#      LUT2_D                      : 3
#      LUT2_L                      : 1
#      LUT3                        : 21
#      LUT3_L                      : 14
#      LUT4                        : 70
#      LUT4_D                      : 1
#      LUT4_L                      : 46
#      MUXCY                       : 106
#      MUXF5                       : 9
#      OR2                         : 3
#      VCC                         : 1
#      XORCY                       : 61
# FlipFlops/Latches                : 123
#      FD                          : 1
#      FDC                         : 13
#      FDCE                        : 18
#      FDE                         : 13
#      FDP                         : 18
#      FDR                         : 59
#      FDS                         : 1
# Clock Buffers                    : 3
#      BUFG                        : 2
#      BUFGP                       : 1
# IO Buffers                       : 16
#      IBUF                        : 4
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                     133  out of   3584     3%  
 Number of Slice Flip Flops:           123  out of   7168     1%  
 Number of 4 input LUTs:               231  out of   7168     3%  
 Number of bonded IOBs:                 17  out of    141    12%  
 Number of GCLKs:                        3  out of      8    37%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 63    |
XLXI_2/x                           | NONE                   | 1     |
XLXN_171(XLXN_17LogicTrst1:O)      | BUFG(*)(XLXI_8/CNT0_3) | 24    |
XLXI_38/Clk_Out1                   | BUFG                   | 35    |