digclk.syr

数字钟的实现

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 1.22 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.22 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: digclk.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "digclk.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "digclk"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : digclk
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : digclk.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/FPGA/VHDL/waitpast/dig_clk_lcd/bskz.vhdl" in Library work.
Architecture behavioral of Entity bskz is up to date.
Compiling vhdl file "F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl" in Library work.
Architecture behavioral of Entity fpq_sound is up to date.
Compiling vhdl file "F:/FPGA/VHDL/waitpast/dig_clk_lcd/FPQ1S.vhdl" in Library work.
Architecture behavioral of Entity fpq1s is up to date.
Compiling vhdl file "F:/FPGA/VHDL/waitpast/dig_clk_lcd/MIN.vhdl" in Library work.
Architecture behavioral of Entity min is up to date.
Compiling vhdl file "F:/FPGA/VHDL/waitpast/dig_clk_lcd/HOUR.vhdl" in Library work.
Architecture behavioral of Entity hour is up to date.
Compiling vhdl file "F:/FPGA/VHDL/waitpast/dig_clk_lcd/s59.vhdl" in Library work.
Architecture behavioral of Entity s59 is up to date.
Compiling vhdl file "F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd" in Library work.
Architecture behavioral of Entity lcd1602 is up to date.
Compiling vhdl file "F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf" in Library work.
Entity <digclk> compiled.
Entity <digclk> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <digclk> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - "F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf" line 14: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf" line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <digclk> analyzed. Unit <digclk> generated.

Analyzing Entity <bskz> (Architecture <behavioral>).
Entity <bskz> analyzed. Unit <bskz> generated.

Analyzing Entity <fpq_sound> (Architecture <behavioral>).
WARNING:Xst:819 - "F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl" line 33: The following signals are missing in the process sensitivity list:
   y.
Entity <fpq_sound> analyzed. Unit <fpq_sound> generated.

Analyzing Entity <fpq1S> (Architecture <behavioral>).
Entity <fpq1S> analyzed. Unit <fpq1S> generated.

Analyzing Entity <MIN> (Architecture <behavioral>).
Entity <MIN> analyzed. Unit <MIN> generated.

Analyzing Entity <HOUR> (Architecture <behavioral>).
Entity <HOUR> analyzed. Unit <HOUR> generated.

Analyzing Entity <s59> (Architecture <behavioral>).
Entity <s59> analyzed. Unit <s59> generated.

Analyzing Entity <LCD1602> (Architecture <behavioral>).
WARNING:Xst:790 - "F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd" line 139: Index value(s) does not match array range, simulation mismatch.
Entity <LCD1602> analyzed. Unit <LCD1602> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <LCD1602>.
    Related source file is "F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd".
WARNING:Xst:1780 - Signal <m> is never used or assigned.
WARNING:Xst:1781 - Signal <cgram<0:15>> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <cgram<18>> is used but never assigned. Tied to value 00101101.
WARNING:Xst:653 - Signal <cgram<21>> is used but never assigned. Tied to value 00101101.
WARNING:Xst:1781 - Signal <cgram<24:30>> is used but never assigned. Tied to default value.
    Found finite state machine <FSM_0> for signal <Current_State>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 7                                              |
    | Inputs             | 0                                              |
    | Outputs            | 7                                              |
    | Clock              | LCD_Clk (rising_edge)                          |
    | Reset              | Reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | set_dlnf                                       |
    | Power Up State     | set_dlnf                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <LCD_Data>.
    Found 1-bit register for signal <LCD_RS>.
    Found 8-bit 31-to-1 multiplexer for signal <$n0005> created at line 139.
    Found 5-bit adder for signal <$n0024> created at line 143.
    Found 8-bit addsub for signal <$n0025>.
    Found 8-bit adder for signal <$n0026> created at line 150.
    Found 5-bit comparator less for signal <$n0027> created at line 142.
    Found 5-bit comparator lessequal for signal <$n0028> created at line 147.
    Found 15-bit comparator less for signal <$n0029> created at line 71.
    Found 9-bit comparator less for signal <$n0030> created at line 84.
    Found 1-bit register for signal <CLK1>.
    Found 1-bit register for signal <Clk_Out>.
    Found 5-bit register for signal <cnt1>.
    Found 15-bit up counter for signal <n1>.
    Found 9-bit up counter for signal <n2>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  11 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   4 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <LCD1602> synthesized.


Synthesizing Unit <s59>.
    Related source file is "F:/FPGA/VHDL/waitpast/dig_clk_lcd/s59.vhdl".
    Found 1-bit register for signal <COUT>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 4-bit adder for signal <$n0008> created at line 31.
    Found 4-bit comparator less for signal <$n0010> created at line 29.
    Found 4-bit comparator less for signal <$n0011> created at line 34.
    Found 4-bit register for signal <CNT0>.
    Found 4-bit up counter for signal <CNT1>.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <s59> synthesized.


Synthesizing Unit <HOUR>.
    Related source file is "F:/FPGA/VHDL/waitpast/dig_clk_lcd/HOUR.vhdl".
    Found 4-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 4-bit adder for signal <$n0005> created at line 31.
    Found 4-bit comparator less for signal <$n0009> created at line 29.
    Found 4-bit register for signal <CNT0>.
    Found 4-bit up counter for signal <CNT1>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <HOUR> synthesized.


Synthesizing Unit <MIN>.
    Related source file is "F:/FPGA/VHDL/waitpast/dig_clk_lcd/MIN.vhdl".
    Found 1-bit register for signal <COUT>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 4-bit adder for signal <$n0008> created at line 32.
    Found 4-bit comparator less for signal <$n0011> created at line 30.
    Found 4-bit comparator less for signal <$n0012> created at line 35.
    Found 4-bit register for signal <CNT0>.
    Found 4-bit up counter for signal <CNT1>.
    Summary: